# Constants
depth     = $(issue)
memSizing = $(issue)/4 + 1 #3i,4i,6i -> 1,2,2
traceMode = "qemusparc"

# Parameters
NoMigration  = false
procsPerNode = 1
pageSize     = 4096

thermSpot   = 'SescSpot'
thermal     = 'SescTherm'
floorplan   = 'layoutDescr'
technology  = 'techParam'

###############################
# Shared Thermal-layout confs #
###############################
[layoutDescr]
blockDescr[0] = "FPWin           0.0025         0.001          0.000          0.000"
blockMatch[0] = "Proc(0)_FPClusterIssueX"
blockDescr[1] = "FPReg           0.0025         0.001          0.0025         0.000"
blockMatch[1] = "Proc(0):rdFPRegEnergy  Proc(0):wrFPRegEnergy"
blockDescr[3] = "IntWin          0.003          0.0015         0.0035         0.001"
blockMatch[3] = "Proc(0)_FXClusterIssueX*"
blockDescr[4] = "IntReg          0.002          0.0015         0.0065         0.001"
blockMatch[4] = "Proc(0):rdIRegEnergy   Proc(0):wrIRegEnergy"
blockDescr[6] = "FPRAT          0.0035         0.0005         0.000          0.0010"
blockMatch[6] = "Proc(0):renameEnergy"
blockDescr[7] = "IntRAT          0.0035         0.0010         0.000          0.0015"
blockMatch[7] = "Proc(0):renameEnergy"
blockDescr[10] = "ROB             0.0025         0.0015         0.0035         0.0025"
blockMatch[10] = "Proc(0):robEnergy"
blockDescr[11] = "Icache          0.0045        0.0015         0.000          0.004"
blockMatch[11] = "P(0)_IL1* P(0)_ITLB*"
blockDescr[12] = "Dcache          0.005         0.0015         0.005          0.004"
blockMatch[12] = "P(0)_DTLB*"
blockDescr[13] = "MSHR            0.0005        0.0015         0.0045         0.004"
blockMatch[13] = "P(0)_DL1_MSHR P(0)_PBuff"
blockDescr[14] = "L2              0.0100        0.0055         0.000          0.0055"
blockMatch[14] = "L2 niceCache"
blockDescr[2] = "FPUnitMult          0.0015          0.001         0.0085         0.000"
blockMatch[2] = "Cluster(0):fpMult"
blockDescr[18] = "FPUnitAlu          0.0020          0.001         0.0065          0.000"
blockMatch[18] = "Cluster(0):fpALU"
blockDescr[19] = "FPUnitDiv          0.0015          0.001         0.005         0.000"
blockMatch[19] = "Cluster(0):fpDiv"
blockDescr[5] = "IntUnitMult         0.0015         0.0005         0.0085         0.0020"
blockMatch[5] = "Cluster(0):iMult"
blockDescr[20] = "IntUnitAlu         0.0015         0.0005         0.0085         0.0015"
blockMatch[20] = "Cluster(0):iALU"
blockDescr[21] = "IntUnitDiv         0.0015         0.0005         0.0085         0.001"
blockMatch[21] = "Cluster(0):iDiv"
blockDescr[9] = "LDQ             0.002          0.0015         0.006          0.0025"
blockMatch[9] = "FULoad(0) FUMemory(0)"
blockDescr[17] = "STQ            0.002          0.0015         0.008          0.0025"
blockMatch[17] = "FUStore(0) FUMemory(0)"
blockDescr[8] = "RAS           0.0005         0.00075         0.003          0.00325"
blockMatch[8] = "BPred(0)_RAS"
blockDescr[16] = "Bpred         0.0030         0.00075         0.000          0.00325"
blockMatch[16] = "BPred(0)_hybrid"
blockDescr[15] = "BTB          0.0035         0.00075         0.000          0.0025"
blockMatch[15] = "BPred(0)_BTB"


# SESCTHERM configuration
[SescTherm]
CyclesPerSample =               20000
initialTemp = 25.0 # Init temperature
ambientTemp = 40
MeshResolutionChip = 0.003
MeshResolutionSpreader = 0.100
MeshResolutionSink = 0.500
TimeIncrement = 0.25
# Fan Velocity (m/s) (typical range 2-8m/s) (assume laminar flow)                                       
# Velocity (LFM) = Volume (CFM) / area (ft^2)
# Velocity (m/s) = Volume (m^3/s) / area (m^2)
FanVelocity = 2.00
ucool = 'ucoolConf'
material[0] = 'Silicon'
material[1] = 'Copper'
material[2] = 'Virtual'
layer[1] = 'layer1'
layer[2] = 'layer2'
layer[3] = 'layer3'
layer[4] = 'layer4'
layer[5] = 'layer5'

[ucoolConf]
Width   = .0001
Height  = .0001
current = 0.400                         
coupledDevices = 12
conductivity = 3.0         # K (W/m*K) Thermal conductivity
Resistivity  = 0.000002857 # ohm meters Electrical Resistivity
seebeck      = 0.00024     # alpha (V/K) Seebeck Coefficient
crossSection = 0.05        # G (Cross-sectional / leg length of the TE elements) (meters)


[Silicon]
density  = 2330
specHeat =  712
conductance = 148
alpha    = 0.0000892

[Copper]
density  = 8933
specHeat = 385
conductance = 401
alpha    =  0.000117

[Virtual]
density     = 0
specHeat    = 0
conductance = 0
alpha       = 0

[layer1]
material  = 'Silicon'
thickness = 0.001

[layer2]
material  = 'Virtual'
thickness = 0

[layer3]
material  = 'Copper'
thickness = 0.002

[layer4]
material  = 'Copper'
thickness = 0.020
heat_spreader = true
heat_spreader_height = 0.020
heat_spreader_width  = 0.020

[layer5]
material  = 'Copper'
thickness = 0.100
heat_sink = true
heat_sink_height = 0.100 
heat_sink_width  = 0.100
heat_sink_fins   = 5
heat_sink_resistance = 0.13

# SESCSPOT configuration
[SescSpot] 
DTMUsed         =               false
ChipThickness   =               0.0005
DTMTempThreshhold=              111.8
ConvectionCapacitance=          140.4
ConvectionResistance=           0.1
HeatsinkLength  =               0.06
HeatsinkThinkness=              0.0069
SpreaderLength  =               0.03
SpreaderThickness=              0.001
InterfaceMaterialThickness=     0.000075

###############################
# clock-panalyzer input       #
###############################
[techParam]
clockTreeStyle = 'htree'        # 1 for Htree or 2 for balHtree
tech       = 70                 # nm
frequency  = 5e9                # Hz
skewBudget = 20                 # in ps
areaOfChip = 200                # in mm^2
loadInClockNode = 20            # in pF
optimalNumberOfBuffer = 3

###############################
# io-panalyzer input          #
###############################
padCapacitance = 1              # in pF
loadCapacitance = 1             # in pF
numberOfioBufferStage = 5       
microstripLength = 10           # in inches

###############################
# logic-panalyzer input       #
###############################
randomLogicStyle = 1            # 1 for Static or 2 for Dynamic
numberOfClusters = 1    
numberofGates = 30000
numberOfFunctions = 4
numberOfFanouts = 1
numberOfFanins = 4

################################
# Temperature Parameters
################################

[ChipSpecs]
chipThickness  = 0.0005    # m
tempThreshold  = 111.8     # C

[HeatSink]
convecC        = 140.4     # J/K
convecR        = 0.1       # K/W
heatsinkSide   = 0.06      # m
heatsinkThick  = 0.069     # m

[HeatSpreader]
spreaderSide   = 0.03      # m
spreaderThick  = 0.001     # m

[InterfaceMaterial]
interfaceThick = 0.000075  # m

[AmbientTemperature]
ambientTemp    = 40        # C
offsetConstant = 273.15    # Kelvin
initialTemp    = 60        # C

################################
# Simulation Parameters
################################

[SimParams]
sampleRate     = 10        # usec
floorPlanFile  = 'scooreX.flp'
hotspotLogFile = 'scooreX.out'
setBinaryLog   = 1
omitLateralR   = 0
dtmUsed        = 0

###############################
#  PROCESSORS CONFIGURATION   #
###############################

[issueX]
archBits       = 32
areaFactor     = ($(issue)*$(depth)+0.1)/16  # Area in relation with alpha264 EV6
issueWrongPath = true
inorder        = false
fetchWidth     = ($(issue)/6+1)*6
instQueueSize  = 2*($(issue)/6+1)*6
issueWidth     = $(issue)
retireWidth    = $(issue)
decodeDelay    = 3
renameDelay    = 3
maxBranches    = 4+6*$(depth)
bb4Cycle       = 1
bpredDelay     = 1
maxIRequests   = 3  # +1 icache hit delay -> 1 outs miss
interClusterLat= 2  # P4 intra +1?
cluster[0]     = 'FXClusterIssueX'
cluster[1]     = 'FPClusterIssueX'
stForwardDelay = 1  # +1 clk from the instruction latency
maxLoads       = 6*$(depth)+30
maxStores      = 4*$(depth)+30
LSQBanks       = 1  # Banked LD/ST Queue 
regFileDelay   = 3
robSize        = 26*$(depth)+48
intRegs        = 48+14*$(depth)
fpRegs         = 32+12*$(depth)
bpred          = 'BPredIssueX'
dataSource     = "DataL1 DL1"
instrSource    = "InstL1 IL1"
enableICache   = true
dtlb           = 'FXDTLB'
itlb           = 'FXITLB'
OSType         = 'std'
minTLBMissDelay= 16 # Min Clk to services a TLB miss (I/D)

[FXDTLB]
deviceType='tlb'
size =  64*8
assoc = 64
bsize = 8
numPorts = $(memSizing)
replPolicy = 'LRU'

[FXITLB]
deviceType = 'tlb'
size  = 32*8
assoc = 32
bsize = 8
numPorts = 1
replPolicy = 'LRU'

[FXClusterIssueX]
blockName   = "IntWin"
winSize      = 12*$(depth)+32 # window number of entries
recycleAt    = 'Execute'      # Recycle entries at : Execute|Retire
schedNumPorts = 4
schedPortOccp = 1
wakeUpNumPorts= 4
wakeUpPortOccp= 1
wakeupDelay   = 3
schedDelay    = 1 # Minimum latency like a intraClusterLat
iStoreLat    = 1
iStoreUnit   = 'STIssueX'
iLoadLat     = 1
iLoadUnit    = 'LDIssueX'
iALULat      = 1
iALUUnit     = 'ALUIssueX'
iBJLat       = 1
iBJUnit      = 'ALUIssueX'
iDivLat      = 12
iDivUnit     = 'ALUIssueX'
iMultLat     = 4
iMultUnit    = 'ALUIssueX'

[FPClusterIssueX]
blockName   = "FPWin"
winSize      = 8*$(depth)+8      # window number of entries
recycleAt    = 'Execute' # Recycle entries at : Execute|Retire
schedNumPorts = 4
schedPortOccp = 1
wakeUpNumPorts= 4
wakeUpPortOccp= 1
wakeupDelay   = 3
schedDelay    = 1 # Minimum latency like a intraClusterLat
fpALULat     = 2
fpALUUnit    = 'FP0IssueX'
fpMultLat    = 4
fpMultUnit   = 'FP0IssueX'
fpDivLat     = 10
fpDivUnit    = 'FP0IssueX'

[STIssueX]
Num = $(STUnits)
Occ = 1

[LDIssueX]
Num = $(LDUnits)
Occ = 1

[ALUIssueX]
Num = (2*$(issue))/4+1
Occ = 1

[FP0IssueX]
Num = (2*$(issue))/5+1
Occ = 1

# Example of crappy static predictor
[BPredTaken]
type = "Static"
btbSize        = 0
btbBsize       = 1
btbAssoc       = 1
btbReplPolicy  = 'LRU'
rasSize        = 1

[BPredIssueX]
type           = "hybrid" 
bpred4Cycle    = 1 # bpred for cycle
BTACDelay      = 0 # no BTAC
l1size         = 1
l2size         = 16*1024
l2Bits         = 1
historySize    = 11
Metasize       = 16*1024
MetaBits       = 2
localSize      = 16*1024
localBits      = 2
btbSize        = 2048
btbBsize       = 1
btbAssoc       = 2
btbReplPolicy  = 'LRU'
rasSize        = 0 # 32 is realistic

[BestBPred]
type           = "ogehl"
BTACDelay      = 0
mtables        = 6       # Number of tables (M)
tsize          = 2*1024  # Size of each table
tbits          = 5       # Bits for each table entry
tcbits         = 7       # Bits for theta updates
btbSize        = 2048
btbBsize       = 1
btbAssoc       = 2
btbReplPolicy  = 'LRU'
rasSize        = 0


###############################

[InstL1]
deviceType  =  'icache'
blockName   = "Icache"
size        =    16*1024
assoc       =        2
bsize       =       64
writePolicy =     'WB'
replPolicy  =    'LRU'
numPorts    =        2
portOccp    =        1
hitDelay    =        2
missDelay   =        0
MSHR        = 'InstL1MSHR'
lowerLevel  =  "L2Cache L2 shared"

[InstL1MSHR]
size = 4
type = 'full'
bsize = 64

[L2Cache]
deviceType   = 'cache'
blockName    = "L2"
size         =1024*1024
assoc        =  8
bsize        = 64
writePolicy  ='WB'
replPolicy   ='LRU'
numPorts     =  1
portOccp     =  1
hitDelay     = 10
missDelay    =  4
MSHR         = 'MSHRL2'
lowerLevel  = "$(L2ll)"

[MSHRL2]
type = 'full'
size = 32
bsize = 64

[PBuff]
deviceType  = 'prefbuff'
streamCache = 'PBuffStream'
buffCache   = 'PBuffBuff'
depth       = 1
missWindow  = 16
maxStride   = 512
hitDelay       = 3
missDelay      = 2
learnHitDelay  = 4
learnMissDelay = 6 
lowerLevel  = "AdvMem MemBus shared"

[PBuffStream]
deviceType  = 'cache'
Size        = 16 * 8 
Assoc       = 16
BSize       = 8
ReplPolicy  = 'LRU'
numPorts    = 2
portOccp    = 3

[PBuffBuff]
deviceType  = 'cache'
Size        = 16 * 1024
Assoc       = 4
BSize       = 32
ReplPolicy  = 'LRU'
numPorts    = 2
portOccp    = 3

[AdvMem]
deviceType  =    'bus'
busWidth    =     64
numPorts    =      1
portOccp    =     32   # 5GHz :  64 (L3)/32 = 2 bytes per cycles -> 10GBytes/s
delay       =      1
lowerLevel  =  "BigMem"
iopins      = true

[BigMem]
deviceType  = 'niceCache'
size        = 1024
assoc       =    1
bsize       =   64
writePolicy = 'WB'
replPolicy  = 'LRU'
numPorts    =     1
portOccp    =     1
hitDelay    =   490   # 5GHz: ~100ns is 500 cycles (10 L1 + L2 miss)
missDelay   =   1600000 # Not valid
MSHR        = "BigMemMSHR"
lowerLevel  = "voidDevice"

[BigMemMSHR]
size = 32
type = 'none'
bsize = 64

[voidDevice]
deviceType  =   'void'

############################
#     BEGIN MIPSEMUL       #
############################

[FileSys]
mount=""

##############################
#     BEGIN TASKSCALAR       #
##############################
[TaskScalar]
VersionSize   = 32          # Version size (HVersion) in bits
SyncOnRestart =  3          # Number of restarts before wait to become safe
MLThreshold   = 8*$(nCPUs)  # Merge Last  Threshold Safe thread
MFThreshold   = $(nCPUs)    # Merge First Threshold Safe thread
IDP           = 'IntPred1'  # Interval Predictor
bsize         = 64          # Versioned cache line size

################################
# IDP: Interval Distribution Predictor (one per processor)
[IntPred1]
deviceType   = 'cache' 
IDPnChildMax = 4     # 4 default value, 0 means no prediction
size         = 32*8  # 32 entries
bSize        = 8
Assoc        = 32
ReplPolicy   = 'LRU'
numPorts     = 1
portOccp     = 1