diff --git a/shared-core/radeon_drm.h b/shared-core/radeon_drm.h
index ffaa46e..2435936 100644
--- a/shared-core/radeon_drm.h
+++ b/shared-core/radeon_drm.h
@@ -677,6 +677,8 @@ typedef struct drm_radeon_indirect {
 #define RADEON_PARAM_VBLANK_CRTC           13   /* VBLANK CRTC */
 #define RADEON_PARAM_FB_LOCATION           14   /* FB location */
 #define RADEON_PARAM_NUM_GB_PIPES          15   /* num GB pipes */
+/* Added with DRM version 1.30. */
+#define RADEON_PARAM_NUM_SAMPLES           16   /* Occlusion query */
 
 typedef struct drm_radeon_getparam {
 	int param;
@@ -732,6 +734,7 @@ typedef struct drm_radeon_setparam {
 #define RADEON_SETPARAM_NEW_MEMMAP 4		/* Use new memory map */
 #define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5    /* PCI GART Table Size */
 #define RADEON_SETPARAM_VBLANK_CRTC 6           /* VBLANK CRTC */
+#define RADEON_SETPARAM_END_QUERY          7    /* occlusion query */
 /* 1.14: Clients can allocate/free a surface
  */
 typedef struct drm_radeon_surface_alloc {
diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 85ae1ce..3fcf9d7 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -313,6 +313,8 @@ typedef struct drm_radeon_private {
 	uint32_t flags;		/* see radeon_chip_flags */
 	unsigned long fb_aper_offset;
 
+	unsigned int query_ring_count;
+
 	int num_gb_pipes;
 	int track_flush;
 	uint32_t chip_family; /* extract from flags */
diff --git a/shared-core/radeon_state.c b/shared-core/radeon_state.c
index 57e3a3b..c4429aa 100644
--- a/shared-core/radeon_state.c
+++ b/shared-core/radeon_state.c
@@ -3100,6 +3100,20 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
 	case RADEON_PARAM_NUM_GB_PIPES:
 		value = dev_priv->num_gb_pipes;
 		break;
+	case RADEON_PARAM_NUM_SAMPLES: {
+		int i;
+		int offset = *(int*)param->value;
+		u32* mainptr = dev_priv->ring_rptr->handle + 0x30 + offset;
+		value = 0;
+
+		for (i = 0; i < dev_priv->num_gb_pipes; i++) {
+			if (*(mainptr + i) == 0xFFFFFFFF) {
+				value = 0xFFFFFFFF;
+				break;
+			} else
+				value += *(mainptr + i);
+		}
+		break; }
 	default:
 		DRM_DEBUG( "Invalid parameter %d\n", param->param );
 		return -EINVAL;
@@ -3160,6 +3174,28 @@ static int radeon_cp_setparam(struct drm_device *dev, void *data, struct drm_fil
 	case RADEON_SETPARAM_VBLANK_CRTC:
 		return radeon_vblank_crtc_set(dev, sp->value);
 		break;
+	case RADEON_SETPARAM_END_QUERY:
+		if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300) {
+			RING_LOCALS
+			uint64_t i;
+			uint32_t offset = sp->value;
+			u32* cardptr = (u32*)RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
+					+ 0x30 + offset;
+			u32* mainptr = dev_priv->ring_rptr->handle
+					+ 0x30 + offset;
+			BEGIN_RING(4 * dev_priv->num_gb_pipes + 2);
+			for (i = 0; i < dev_priv->num_gb_pipes; i++) {
+				OUT_RING_REG(R500_SU_REG_DEST, i);
+				OUT_RING_REG(R300_ZB_ZPASS_ADDR, (u32)(cardptr + i));
+				*(mainptr + i) = 0xFFFFFFFF;
+			}
+			OUT_RING_REG(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
+			ADVANCE_RING();
+		} else {
+			DRM_ERROR("Occlusion query requested for pre-r300 chipset\n");
+			return -EINVAL;
+		}
+		break;
 	default:
 		DRM_DEBUG("Invalid parameter %d\n", sp->param);
 		return -EINVAL;