perl decode-dimms.pl PC DIMM Serial Presence Detect Tester/Decoder By Philip Edelbrock, Christian Zuckschwerdt, Burkart Lingner, Jean Delvare and others Version 2.10.0 Decoding EEPROM: /sys/bus/i2c/drivers/eeprom/0-0051 Guessing DIMM is in bank 2 ---=== The Following is Required Data and is Applicable to all DIMM Types ===---EEPROM Checksum of bytes 0-62 OK (0x93) # of bytes written to SDRAM EEPROM 128 Total number of bytes in EEPROM 256 Fundamental Memory type DDR SDRAM Number of Row Address Bits (SDRAM only) 13 Number of Col Address Bits (SDRAM only) 10 Number of Module Rows 2 Data Width (SDRAM only) 64 Module Interface Signal Levels SSTL 2.5 Cycle Time (SDRAM) highest CAS latency 5ns Maximum module speed DDR 400MHz (PC3200) Access Time (SDRAM) 6ns Module Configuration Type No Parity Refresh Type Self Refreshing Refresh Rate Reduced (7.8uS) Primary SDRAM Component Bank Config No Bank2 OR Bank2 = Bank1 width Primary SDRAM Component Widths 8 Error Checking SDRAM Component Bank Config No Bank2 OR Bank2 = Bank1 width Error Checking SDRAM Component Widths Undefined! Min Clock Delay for Back to Back Random Access 1 ---=== The Following Apply to SDRAM DIMMs ONLY ===--- Burst lengths supported Burst Length = 2 Burst Length = 4 Burst Length = 8 Number of Device Banks 4 Supported CAS Latencies CAS Latency = 3 CAS Latency = 4 Supported CS Latencies CS Latency = 0 Supported WE Latencies WE Latency = 1 SDRAM Module Attributes Differential Clock Input SDRAM Device Attributes (General) Lower VCC Tolerance: 10% Upper VCC Tolerance: 10% SDRAM Cycle Time (2nd highest CAS) 6nS SDRAM Access from Clock Time (2nd highest CAS) 7nS ---=== The Following are Optional (may be Bogus) ===--- SDRAM Cycle Time (3rd highest CAS) Undefined! SDRAM Access from Clock Time (3rd highest CAS) Undefined! ---=== The Following are Required (for SDRAMs) ===--- Minimum Row Precharge Time 60nS Row Active to Row Active Min 40nS RAS to CAS Delay 60nS Min RAS Pulse Width 40nS ---=== The Following are Required and Apply to ALL DIMMs ===--- Row Densities 256 MByte ---=== The Following are Proposed and Apply to SDRAM DIMMs ===--- Command and Address Signal Setup Time 6nS Command and Address Signal Hold Time 6nS Data Signal Setup Time 4nS Data Signal Hold Time 4nS SPD Revision code 0 Manufacturer Corsair Manufacturing Location Code 0x01 Part Number CMX512-3200C2 Revision Code 0x0000 Manufacturing Date 0x0000 Assembly Serial Number 0x00000000 Intel Specification for Frequency Undefined! Intel Spec Details for 100MHz Support Intel Concurrent AutoPrecharge CAS Latency = 2 CAS Latency = 3 Junction Temp A (90 degrees C) CLK 3 Connected CLK 2 Connected CLK 1 Connected CLK 0 Connected Double Sided DIMM Decoding EEPROM: /sys/bus/i2c/drivers/eeprom/0-0052 Guessing DIMM is in bank 3 ---=== The Following is Required Data and is Applicable to all DIMM Types ===---EEPROM Checksum of bytes 0-62 OK (0xAB) # of bytes written to SDRAM EEPROM 128 Total number of bytes in EEPROM 256 Fundamental Memory type DDR SDRAM Number of Row Address Bits (SDRAM only) 13 Number of Col Address Bits (SDRAM only) 10 Number of Module Rows 1 Data Width (SDRAM only) 64 Module Interface Signal Levels SSTL 2.5 Cycle Time (SDRAM) highest CAS latency 5ns Maximum module speed DDR 400MHz (PC3200) Access Time (SDRAM) 6ns Module Configuration Type No Parity Refresh Type Self Refreshing Refresh Rate Reduced (7.8uS) Primary SDRAM Component Bank Config No Bank2 OR Bank2 = Bank1 width Primary SDRAM Component Widths 8 Error Checking SDRAM Component Bank Config No Bank2 OR Bank2 = Bank1 width Error Checking SDRAM Component Widths Undefined! Min Clock Delay for Back to Back Random Access 1 ---=== The Following Apply to SDRAM DIMMs ONLY ===--- Burst lengths supported Burst Length = 2 Burst Length = 4 Burst Length = 8 Number of Device Banks 4 Supported CAS Latencies CAS Latency = 4 Supported CS Latencies CS Latency = 0 Supported WE Latencies WE Latency = 1 SDRAM Module Attributes Differential Clock Input SDRAM Device Attributes (General) Lower VCC Tolerance: 10% Upper VCC Tolerance: 10% SDRAM Cycle Time (2nd highest CAS) Undefined! SDRAM Access from Clock Time (2nd highest CAS) Undefined! ---=== The Following are Optional (may be Bogus) ===--- SDRAM Cycle Time (3rd highest CAS) Undefined! SDRAM Access from Clock Time (3rd highest CAS) Undefined! ---=== The Following are Required (for SDRAMs) ===--- Minimum Row Precharge Time 60nS Row Active to Row Active Min 40nS RAS to CAS Delay 60nS Min RAS Pulse Width 40nS ---=== The Following are Required and Apply to ALL DIMMs ===--- Row Densities 256 MByte ---=== The Following are Proposed and Apply to SDRAM DIMMs ===--- Command and Address Signal Setup Time 6nS Command and Address Signal Hold Time 6nS Data Signal Setup Time 4nS Data Signal Hold Time 4nS SPD Revision code 0 Manufacturer Level One Communication Manufacturing Location Code 0x00 Part Number Undefined Revision Code 0x0000 Manufacturing Date 0x0000 Assembly Serial Number 0x00000000 Intel Specification for Frequency Undefined! Intel Spec Details for 100MHz Support Junction Temp B (100 degrees C) Single Sided DIMM Number of SDRAM DIMMs detected and decoded: 2