Index: pcsx2/R5900OpcodeImpl.cpp
===================================================================
--- pcsx2/R5900OpcodeImpl.cpp	(revision 594)
+++ pcsx2/R5900OpcodeImpl.cpp	(working copy)
@@ -325,8 +325,8 @@
 
 	if (!_Rt_) return;
 	memRead32(addr & ~3, &mem);
-	cpuRegs.GPR.r[_Rt_].UD[0] =	(cpuRegs.GPR.r[_Rt_].UL[0] & LWL_MASK[shift]) | 
-								(mem << LWL_SHIFT[shift]);
+	cpuRegs.GPR.r[_Rt_].SD[0] =	(cpuRegs.GPR.r[_Rt_].UL[0] & LWL_MASK[shift]) | 
+								(s32)(mem << LWL_SHIFT[shift]);
 
 	/*
 	Mem = 1234.  Reg = abcd
@@ -338,7 +338,7 @@
 	*/
 }
 
-u32 LWR_MASK[4] = { 0, 0xff000000, 0xffff0000, 0xffffff00 };
+u64 LWR_MASK[4] = { 0ULL, 0xffffffffff000000ULL, 0xffffffffffff0000ULL, 0xffffffffffffff00ULL };
 u32 LWR_SHIFT[4] = { 0, 8, 16, 24 };
 
 void LWR() {
@@ -348,8 +348,8 @@
 
 	if (!_Rt_) return;
 	memRead32(addr & ~3, &mem);
-	cpuRegs.GPR.r[_Rt_].UD[0] =	(cpuRegs.GPR.r[_Rt_].UL[0] & LWR_MASK[shift]) | 
-								(mem >> LWR_SHIFT[shift]);
+	cpuRegs.GPR.r[_Rt_].SD[0] =	(cpuRegs.GPR.r[_Rt_].SD[0] & LWR_MASK[shift]) | 
+								(s32)(mem >> LWR_SHIFT[shift]);
 
 	/*
 	Mem = 1234.  Reg = abcd