;
; HC9S12 Register mappings
; 
; Multiplexed External Bus Interface
MEBI_BASE equ   $0000
PORTA     equ   $0000 ; Port A data 
PORTB     equ   $0001 ; Port B data
DDRA      equ   $0002 ; Port A data direction
DDRB      equ   $0003 ; Port B data direction
PORTE     equ   $0008 ; Port E data
DDRE      equ   $0009 ; Port E data direction
PEAR      equ   $000A ; Port E assignment
MODE      equ   $000B ; Operating mode
PUCR      equ   $000C ; Pull control
RDRIV     equ   $000D ; Reduced drive
EBICTL    equ   $000E ; External bus interface control
PORTK     equ   $0032 ; Port K data
DDRK      equ   $0033 ; Port K data direction
; Memory Map Control Module
MMC_BASE  equ   $0010
INITRM    equ   $0010  ; Initialize internal RAM position
INITRG    equ   $0011  ; Initialize internal Register position
INITEE    equ   $0012  ; Initialize internal EEPROM position
MISC      equ   $0014  ; Misc. system control
MEMSIZE0  equ   $001C  ; Memory size reg. 0
MEMSIZE1  equ   $001D  ; Memory size reg. 1
INTCR     equ   $001E  ;
PPAGE     equ   $0020  ; Program page index
; Interrupts
INT_BASE  equ   $0015
ITCR      equ   $0015
ITEST     equ   $0016
HPRIO     equ   $001F
; Voltage Regulator
VREG_BASE equ   $0019
VREGCTTL  equ   $0019
; Miscellaneous Peripherals
PARTID    equ   $001A             ; [2] Device ID
PARTIDH   equ   $001A            ; PARTID high byte
PARTIDL   equ   $001B    ; PARTID low byte
; Debug
DBG_BASE  equ   $0020
DBGC1     equ   $0020
DBGSC     equ   $0021
DBGTBH    equ   $0022
DBGTBL    equ   $0023
DBGCNT    equ   $0024
DBGCCX    equ   $0025
DBGCC     equ   $0026  ; [2]
DBGCCH    equ   $0026
DBGCCL    equ   $0027
DBGC2     equ   $0028
DBGC3     equ   $0029
DBGCAX    equ   $002A
DBGCA     equ   $002B
DBGCAH    equ   $002B
DBGCAL    equ   $002C
DBGCBX    equ   $002D
DBGCB     equ   $002E
DBGCBH    equ   $002E
DBGCBL    equ   $002F
; Clock and Reset Generator Module
CRG_BASE  equ   $0034
SYNR      equ   $0034  ; PLL multiplier
REFDV     equ   $0035  ; PLL divisor
CTFLG     equ   $0036  ; Reserved
CRGFLG    equ   $0037  ; Provides CRG status and flags
CRGINT    equ   $0038  ; CRG interrupt enable
CLKSEL    equ   $0039  ; CRG clock selection
PLLCTL    equ   $003A  ; Control PLL functionality
RTICTL    equ   $003B  ; Select timeout period for RTI interrupt
COPCTL    equ   $003C  ; Control watchdog
FORBYP    equ   $003D  ; Reserved
CTCTL     equ   $003E  ; Reserved
ARMCOP    equ   $003F  ; Restart watchdog timeout period
; Timer Module
TIM_BASE  equ   $0040
TIOS      equ   $0040  ; Ch.0-7 Input capture/output compare select 
CFORC     equ   $0041  ; Ch.0-7 Forced timer compare
OC7M      equ   $0042  ; ??
OC7D      equ   $0043  ; ??
TCNT      equ   $0044  ; [2] Timer count
TCNTH     equ   $0044  ; TCNT high byte
TCNTL     equ   $0045  ; TCNT low byte
TSCR1     equ   $0046  ; Control timer module operating mode
TTOV      equ   $0047  ; Ch.0-7 toggle on overflow
TCTL1     equ   $0048  ; Ch.4-7 action on successful output compare
TCTL2     equ   $0049  ; Ch.0-3 action on successful output compare
TCTL3     equ   $004A  ; Ch.4-7 input compare edge detection
TCTL4     equ   $004B  ; Ch.0-3 input compare edge detection
TIE       equ   $004C  ; Ch.0-7 timer enable
TSCR2     equ   $004D  ; Control timer module system
TFLG1     equ   $004E  ; Ch.0-7 timer interrupt flags
TFLG2     equ   $004F  ; Timer overflow interrupt flag
TC0       equ   $0050  ; [2] Ch.0 input capture/output compare data
TC0H      equ   $0050  ; TC0 high byte
TC0L      equ   $0051  ; TC0 low byte
TC1       equ   $0052  ; [2] Ch.1 input capture/output compare data
TC1L      equ   $0052  ; TC1 high byte
TC1H      equ   $0053  ; TC1 low byte
TC2       equ   $0054  ; [2] Ch.2 input capture/output compare data
TC2H      equ   $0054  ; TC2 high byte
TC2L      equ   $0055  ; TC2 low byte
TC3       equ   $0056  ; [2] Ch.3 input capture/output compare data
TC3H      equ   $0056  ; TC3 high byte
TC3L      equ   $0057  ; TC3 low byte
TC4       equ   $0058  ; [2] Ch.4 input capture/output compare data
TC4H      equ   $0058  ; TC4 high byte
TC4L      equ   $0059  ; TC4 low byte
TC5       equ   $005A  ; [2] Ch.5 input capture/output compare data
TC5H      equ   $005A  ; TC5 high byte
TC5L      equ   $005B  ; TC5 low byte
TC6       equ   $005C  ; [2] Ch.6 input capture/output compare data
TC6H      equ   $005C  ; TC6 high byte
TC6L      equ   $005D  ; TC6 low byte
TC7       equ   $005E  ; [2] Ch.7 input capture/output compare data
TC7H      equ   $005E  ; TC7 high byte
TC7L      equ   $005F  ; TC7 low byte
PACTL     equ   $0060  ; Pulse accumulator control
PAFLG     equ   $0061  ; PA overflow and input edge flags
PACNT     equ   $0062  ; [2] Pulse accumulator count
PACNTH    equ   $0062  ; PACNT high byte
PACNTL    equ   $0063  ; PACNT low byte
TIMTST    equ   $006D  ; Reserved
; Analog to Digital Converter Module
ATD_BASE  equ   $0080
ATDCTL0   equ   $0080  ; Reserved
ATDCTL1   equ   $0081  ; Reserved
ATDCTL2   equ   $0082  ; Control power down, interrupt, ext. trigger
ATDCTL3   equ   $0083  ; Control conversion length, fifo, freeze mode
ATDCTL4   equ   $0084  ; Control conversion clk, sample time, res.
ATDCTL5   equ   $0085  ; Control conversion type and channels sampled
ATDSTAT0  equ   $0086  ; R/O, seq. complete, overrun flags, conv. cnt
ATDTEST0  equ   $0088  ; Reserved
ATDTEST1  equ   $0089  ; Enable special channel conversions  
ATDSTAT1  equ   $008B  ; Ch.0-7 conversion complete flags  
ATDDIEN   equ   $008D  ; Ch.0-7 digital input enable
PORTAD    equ   $008F  ; Ch.0-7 digital input data
ATDDR0    equ   $0090  ; [2] Ch.0 analog data
ATDDR0H   equ   $0090  ; ATDDR0 high byte
ATDDR0L   equ   $0091  ; ATDDR0 low byte
ATDDR1    equ   $0092  ; [2] Ch.1 analog data
ATDDR1H   equ   $0092  ; ATDDR1 high byte
ATDDR1L   equ   $0093  ; ATDDR1 low byte
ATDDR2    equ   $0094  ; [2] Ch.2 analog data
ATDDR2H   equ   $0094  ; ATDDR2 high byte
ATDDR2L   equ   $0095  ; ATDDR2 low byte
ATDDR3    equ   $0096  ; [2] Ch.3 analog data
ATDDR3H   equ   $0096  ; ATDDR3 high byte
ATDDR3L   equ   $0097  ; ATDDR3 low byte
ATDDR4    equ   $0098  ; [2] Ch.4 analog data
ATDDR4H   equ   $0098  ; ATDDR4 high byte
ATDDR4L   equ   $0099  ; ATDDR4 low byte
ATDDR5    equ   $009A  ; [2] Ch.5 analog data
ATDDR5H   equ   $009A  ; ATDDR5 high byte
ATDDR5L   equ   $009B  ; ATDDR5 low byte
ATDDR6    equ   $009C  ; [2] Ch.6 analog data
ATDDR6H   equ   $009C  ; ATDDR6 high byte
ATDDR6L   equ   $009D  ; ATDDR6 low byte
ATDDR7    equ   $009E  ; [2] Ch.7 analog data
ATDDR7H   equ   $009E  ; ATDDR7 high byte
ATDDR7L   equ   $009F  ; ATDDR7 low byte
; Serial Communication Interface Module 
SCI_BASE  equ   $00C8
SCIBD     equ   $00C8  ; [2] SCI baud rate selection
SCIBDH    equ   $00C8  ; SCIBD high byte
SCIBDL    equ   $00C9  ; SCIBD low byte
SCICR1    equ   $00CA  ; Control various aspects of the SCI module
SCICR2    equ   $00CB  ; Control various aspects of the SCI module
SCISR1    equ   $00CC  ; Maintain SCI module status
SCISR2    equ   $00CD  ; Maintain SCI module status
SCIDR     equ   $00CE  ; [2] Transmit or receive data
SCIDRH    equ   $00CE  ; Holds 9th bit if configured for 9bit data
SCIDRL    equ   $00CF  ; Transmitted or received data byte
; Serial Peripheral Interface Module
SPI_BASE  equ   $00D8
SPICR1    equ   $00D8  ; Control various aspects of SPI module
SPICR2    equ   $00D9  ; Control various aspects of SPI module
SPIBR     equ   $00DA  ; Select SPI module baud rate
SPISR     equ   $00DB  ; SPI module status
SPIDR     equ   $00DC  ; Transmitted or received data byte
; Pulse Width Modulator Module
PWM_BASE  equ   $00E0
PWME      equ   $00E0  ; Ch.0-5 enable
PWMPOL    equ   $00E1  ; Ch.0-5 starting polarity
PWMCLK    equ   $00E2  ; Ch.0-5 clock source selection
PWMPRCLK  equ   $00E3  ; Ch.0-5 prescale clock source selection
PWMCAE    equ   $00E4  ; Ch.0-5 center align enable
PWMCTL    equ   $00E5  ; Various controls from PWM module
PWMTST    equ   $00E6  ; Reserved
PWMPRSC   equ   $00E7  ; Reserved
PWMSCLA   equ   $00E8  ; Used to scale clock A to clock SA
PWMSCLB   equ   $00E9  ; Used to scale clock B to clock SB
PWMSCNTA  equ   $00EA  ; Reserved
PWMSCNTB  equ   $00EB  ; Reserved
PWMCNT0   equ   $00EC  ; Ch.0 count (0-PWMPER0)
PWMCNT1   equ   $00ED  ; Ch.1 count (0-PWMPER1)
PWMCNT2   equ   $00EE  ; Ch.2 count (0-PWMPER2)
PWMCNT3   equ   $00EF  ; Ch.3 count (0-PWMPER3)
PWMCNT4   equ   $00F0  ; Ch.4 count (0-PWMPER4)
PWMCNT5   equ   $00F1  ; Ch.5 count (0-PWMPER5)
PWMPER0   equ   $00F2  ; Ch.0 output period
PWMPER1   equ   $00F3  ; Ch.1 output period
PWMPER2   equ   $00F4  ; Ch.2 output period
PWMPER3   equ   $00F5  ; Ch.3 output period
PWMPER4   equ   $00F6  ; Ch.4 output period
PWMPER5   equ   $00F7  ; Ch.5 output period
PWMDTY0   equ   $00F8  ; Ch.0 duty cycle
PWMDTY1   equ   $00F9  ; Ch.1 duty cycle
PWMDTY2   equ   $00FA  ; Ch.2 duty cycle
PWMDTY3   equ   $00FB  ; Ch.3 duty cycle
PWMDTY4   equ   $00FC  ; Ch.4 duty cycle
PWMDTY5   equ   $00FD  ; Ch.5 duty cycle
PWMSDN    equ   $00FE  ; Control emegency shutdown
; Port Integration Module
PIM_BASE  equ   $0240
PTT       equ   $0240  ; Port T I/O
PTIT      equ   $0241  ; Port T Input
DDRT      equ   $0242  ; Port T Data Direction
RDRT      equ   $0243  ; Port T Reduced Drive
PERT      equ   $0244  ; Port T Pull Device Enable
PPST      equ   $0245  ; Port T Polarity Select
MODRR     equ   $0247  ; Port T Module Routing
PTS       equ   $0248  ; Port S I/O
PTIS      equ   $0249  ; Port S Input
DDRS      equ   $024A  ; Port S Data Direction
RDRS      equ   $024B  ; Port S Reduced Drive
PERS      equ   $024C  ; Port S Pull Device Enable
PPSS      equ   $024D  ; Port S Polarity Select
WOMS      equ   $024E  ; Port S Wired-OR Mode
PTM       equ   $0250  ; Port M I/O
PTIM      equ   $0251  ; Port M Input
DDRM      equ   $0252  ; Port M Data Direction
RDRM      equ   $0253  ; Port M Reduced Drive
PERM      equ   $0254  ; Port M Pull Device Enable
PPSM      equ   $0255  ; Port M Polarity Select
WOMM      equ   $0256  ; Port M Wired-OR Mode
PTP       equ   $0258  ; Port P I/O
PTIP      equ   $0259  ; Port P Input
DDRP      equ   $025A  ; Port P Data Direction
RDRP      equ   $025B  ; Port P Reduced Drive
PERP      equ   $025C  ; Port P Pull Device Enable
PPSP      equ   $025D  ; Port P Polarity Select
PIEP      equ   $025E  ; Port P Interrupt Enable
PIFP      equ   $025F  ; Port P Interrupt Flag
PTJ       equ   $0268  ; Port J I/O
PTIJ      equ   $0269  ; Port J Input
DDRJ      equ   $026A  ; Port J Data Direction
RDRJ      equ   $026B  ; Port J Reduced Drive
PERJ      equ   $026C  ; Port J Pull Device Enable
PPSJ      equ   $026D  ; Port J Polarity Select
PIEJ      equ   $026E  ; Port J Interrupt Enable
PIFJ      equ   $026F  ; Port J Interrupt Flag
PTAD      equ   $0270  ; Port AD I/O
PTIAD     equ   $0271  ; Port AD Input
DDRAD     equ   $0272  ; Port AD Data Direction
RDRAD     equ   $0273  ; Port AD Reduced Drive
PERAD     equ   $0274  ; Port AD Pull Device Enable
PPSAD     equ   $0275  ; Port AD Polarity Select

; Constants
ST_UP   equ     $00
ST_HOLD equ     $01
ST_RLS  equ     $02
ST_DN   equ     $03
ST_IDLE equ     $04
ST_WAKE equ     $05

; Variables
        org     $3800
lastpb  rmb     1        
red     rmb     1
green   rmb     1
blue    rmb     1
inred   rmb     1
ingreen rmb     1
inblue  rmb     1

; Init
        org     $8000
system_init:
        sei                     ; Disable interrupts
        movb    #$00,INITRG     ; Map registers to $0000
        movb    #$39,INITRM     ; Map RAM to $3800 (size $07FF)
        lds     #$4000          ; Initialize stack to top of RAM
        bclr    CLKSEL,$80      ; Disengage PLL
        bset    PLLCTL,$40      ; Enable PLL
        movb    #$02,SYNR       ; PLL multiplier 2
        movb    #$00,REFDV      ; PLL divisor 0
        nop                     ; Let things settle for a couple clocks
        nop
pll_wait:
        brclr   CRGFLG,$08,pll_wait ; Wait for PLL to fully stablize
        bset    CLKSEL,$80      ; Reengage PLL
        movb    #$40,COPCTL     ; Disable watchdog timer
; Setup
; SCI
        movw    #$009C,SCIBD    ; SCI baud rate 9600
        movb    #$00,SCICR1     ; Normal mode, no parity
        movb    #$0C,SCICR2     ; Enable TX/RX, no interrupts
; RTI
        movb    #$50,RTICTL     ; Fire RTI every 2.048ms
        bset    CRGFLG,$80      ; Clear RTI flag
        ;bset    CRGINT,$80      ; Enable RTI
; GPIO
        ;movb    #$03,DDRT       ; PT0-1 digital out (LEDs)
        ;movb    #$C0,ATDDIEN    ; AD6-7 digital in (push buttons)
; ATD
        movb    #$80,ATDCTL2    ; Enable ATD
        movb    #$00,ATDCTL3    ; 1 conversion/sequence
        movb    #$60,ATDCTL4    ; 10bit,LJ,unsigned,2clk/conversion,ATD Clock = Bus/16
; PWM
        movb    #$0F,MODRR      ; PWM0 -> PT0
        movb    #$0F,DDRT       ; PT0 as output
        movb    #$0F,PWME       ; Enable PWM0
        movb    #$0F,PWMPOL     ; Start low
        movb    #$00,PWMCLK     ; Use PWM Clk A
        movb    #$44,PWMPRCLK   ; PWM Clk A = Bus/16
        ;movb    #$80,PWMSCLA
        movb    #$00,PWMCAE     ; left align output
        movb    #$FF,PWMPER1    ; Full 8bit period
        movb    #$FF,PWMPER2    ; Full 8bit period
        movb    #$FF,PWMPER3    ; Full 8bit period
        clr     PWMCNT1         ; clear count
        clr     PWMCNT2         ; clear count
        clr     PWMCNT3         ; clear count

; Initialize variables
        clr     lastpb
        movb    #$FF,red
        movb    #$00,green
        movb    #$00,blue
        movb    #ST_DN,inred
        movb    #ST_UP,ingreen
        movb    #ST_IDLE,inblue
        cli                     ; Reenable interrupts
;Program
main:
chkreddn:
        ldaa    inred
        cmpa    #ST_DN
        bne     chkredup
        dec     red
        bne     chkgreendn
        movb    #ST_IDLE,inred
        bra     chkgreendn
chkredup:
        cmpa    #ST_UP
        bne     chkredwake
        inc     red
        ldaa    red
        cmpa    #$FF
        bne     chkgreendn
        movb    #ST_DN,inred
        movb    #ST_WAKE,inblue
chkredwake:
        cmpa    #ST_WAKE
        bne     chkgreendn
        movb    #ST_UP,inred
chkgreendn:
        ldaa    ingreen
        cmpa    #ST_DN
        bne     chkgreenup
        dec     green
        bne     chkbluedn
        movb    #ST_IDLE,ingreen
        bra     chkbluedn
chkgreenup:
        cmpa    #ST_UP
        bne     chkgreenwake
        inc     green
        ldaa    green
        cmpa    #$FF
        bne     chkbluedn
        movb    #ST_DN,ingreen
        movb    #ST_WAKE,inred
chkgreenwake:
        cmpa    #ST_WAKE
        bne     chkbluedn
        movb    #ST_UP,ingreen
chkbluedn:
        ldaa    inblue
        cmpa    #ST_DN
        bne     chkblueup
        dec     blue
        bne     done
        movb    #ST_IDLE,inblue
        bra     done
chkblueup:
        cmpa    #ST_UP
        bne     chkbluewake
        inc     blue
        ldaa    blue
        cmpa    #$FF
        bne     done
        movb    #ST_DN,inblue
        movb    #ST_WAKE,ingreen
chkbluewake:
        cmpa    #ST_WAKE
        bne     done
        movb    #ST_UP,inblue
done:
        ldaa    red
        jsr     putbyte
        staa    PWMDTY0
        ldaa    green
        jsr     putbyte
        staa    PWMDTY1
        ldaa    blue
        jsr     putbyte
        staa    PWMDTY2
        ldaa    #$20
        jsr     putchar
        ldaa    inred
        jsr     putbyte
        ldaa    ingreen
        jsr     putbyte
        ldaa    inblue
        jsr     putbyte
        ldaa    #$0D
        jsr     putchar

        ldy     #$FF
sleep1:
;        ldx    #$FFFF
;sleep2:
;        dex
;        bne     sleep2
        dey
        bne     sleep1
        jmp     main

        movb    #$80,ATDCTL5
wait:
        brclr   ATDSTAT0,#$80,wait
        ldd     ATDDR0
        tfr     B,A
        jsr     putbyte
        ldaa    #$0D
        jsr     putchar
        stab    PWMDTY0
        stab    PWMDTY1
        stab    PWMDTY2
        stab    PWMDTY3
        jmp     main

putchar:
        brclr   SCISR1,#$40,putchar
        staa    SCIDRL
        rts

putbyte:
        psha
        lsra
        lsra
        lsra
        lsra
        cmpa    #$09
        ble     pbnoinc1
        adda    #$07
pbnoinc1:
        adda    #$30
        jsr     putchar
        ldaa    0,SP
        anda    #$0F
        cmpa    #$09
        ble     pbnoinc2
        adda    #$07
pbnoinc2:
        adda    #$30
        jsr     putchar
        pula
        rts

putstring:
        ldx     2,SP+
psloop:        
        ldaa    1,X+
        beq     psdone
        jsr     putchar
        bra     psloop
psdone:
        pshd
        rts

getchar:
        brclr   SCISR1,#$20,getchar
        ldaa    SCIDRL
        rts
        
; RTI ISR
rti_isr:
        bset    CRGFLG,$80      ; clear interrupt
        ldaa    PORTAD
        cmpa    lastpb
        beq     rti_exit
        staa    lastpb
        lsra
        lsra
        lsra
        lsra
        lsra
        lsra
        staa    PTT
rti_exit:
        rti
; Catch-all interrupt routine
BadInt:
	rti
; Interrupt vector
        org     $FF8A
        fdb     BadInt  ;$FF8A: VREG LVI
        fdb     BadInt  ;$FF8C: PWM emergency shutdown
        fdb     BadInt  ;$FF8E: PortP
        fdb     BadInt  ;$FF90: Reserved
        fdb     BadInt  ;$FF92: Reserved
        fdb     BadInt  ;$FF94: Reserved
        fdb     BadInt  ;$FF96: Reserved
        fdb     BadInt  ;$FF98: Reserved
        fdb     BadInt  ;$FF9A: Reserved
        fdb     BadInt  ;$FF9C: Reserved
        fdb     BadInt  ;$FF9E: Reserved
        fdb     BadInt  ;$FFA0: Reserved
        fdb     BadInt  ;$FFA2: Reserved
        fdb     BadInt  ;$FFA4: Reserved
        fdb     BadInt  ;$FFA6: Reserved
        fdb     BadInt  ;$FFA8: Reserved
        fdb     BadInt  ;$FFAA: Reserved
        fdb     BadInt  ;$FFAC: Reserved
        fdb     BadInt  ;$FFAE: Reserved
        fdb     BadInt  ;$FFB0: CAN transmit
        fdb     BadInt  ;$FFB2: CAN receive
        fdb     BadInt  ;$FFB4: CAN errors
        fdb     BadInt  ;$FFB6: CAN wake-up
        fdb     BadInt  ;$FFB8: FLASH
        fdb     BadInt  ;$FFBA: Reserved
        fdb     BadInt  ;$FFBC: Reserved
        fdb     BadInt  ;$FFBE: Reserved
        fdb     BadInt  ;$FFC0: Reserved
        fdb     BadInt  ;$FFC2: Reserved
        fdb     BadInt  ;$FFC4: CRG self-clock-mode
        fdb     BadInt  ;$FFC6: CRG PLL Lock
        fdb     BadInt  ;$FFC8: Reserved
        fdb     BadInt  ;$FFCA: Reserved
        fdb     BadInt  ;$FFCC: Reserved
        fdb     BadInt  ;$FFCE: PORTJ
        fdb     BadInt  ;$FFD0: Reserved
        fdb     BadInt  ;$FFD2: ATD
        fdb     BadInt  ;$FFD4: Reserved
        fdb     BadInt  ;$FFD6: SCI Serial System
        fdb     BadInt  ;$FFD8: SPI Serial Transfer Complete
        fdb     BadInt  ;$FFDA: Pulse Accumulator Input Edge
        fdb     BadInt  ;$FFDC: Pulse Accumulator Overflow
        fdb     BadInt  ;$FFDE: Timer Overflow
        fdb     BadInt  ;$FFE0: Standard Timer Channel 7
        fdb     BadInt  ;$FFE2: Standard Timer Channel 6
        fdb     BadInt  ;$FFE4: Standard Timer Channel 5
        fdb     BadInt  ;$FFE6: Standard Timer Channel 4
        fdb     BadInt  ;$FFE8: Standard Timer Channel 3
        fdb     BadInt  ;$FFEA: Standard Timer Channel 2
        fdb     BadInt  ;$FFEC: Standard Timer Channel 1
        fdb     BadInt  ;$FFEE: Standard Timer Channel 0
        fdb     rti_isr ;$FFF0: Real Time Interrupt (RTI)
        fdb     BadInt  ;$FFF2: IRQ (External Pin or Parallel I/O) (IRQ)
        fdb     BadInt  ;$FFF4: XIRQ (Pseudo Non-Maskable Interrupt) (XIRQ)
        fdb     BadInt  ;$FFF6: Software Interrupt (SWI)
        fdb     BadInt  ;$FFF8: Illegal Opcode Trap ()
        fdb     system_init ;$FFFA: COP Failure (Reset) ()
        fdb     BadInt  ;$FFFC: Clock Monitor Fail (Reset) ()
        fdb     system_init ;$FFFE: /RESET

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