*  Intel Chips         SIMD Instruction Set
 *  Pentium                     None
 *  Pentium Pro                 None
 *  Pentium MMX                 MMX
 *  Pentium II                  MMX
 *  Pentium III                 SSE
 *  Pentium IV                  SSE2
 *  Pentium IV (Prescott)       SSE3
 *  Pentium IV Xeon (EM64T)     SSE3
 *
 *  AMD Chips           SIMD Instruction Set
 *  AMD K6                      MMX
 *  AMD K6-2                    3D Now
 *  AMD K6-III                  Extended 3D Now
 *  Athalon                     3D Now
 *  Athalon XP                  SSE
 *  AMD 64                      SSE2
 *  AMD 64 (rev. E)             SSE3
 *  AMD 64 X2                   SSE3
 *
 *  AMD SIMD Instruction Sets Includes
 *  3D Now                      MMX
 *  Advanced/Extended 3D Now    MMX
 *  3D Now Pro                  SSE
 *
 *
 *  Data Alignement (required for optimal performance):
 *  MMX ( 64 bits /  8 bytes)   gcc             __attribute__ ((aligned (8)))
 *                              MS Visual C++   __declspec (align (8))
 *  SSE (128 bits / 16 bytes)   gcc             __attribute__ ((aligned (16)))
 *                              MS Visual C++   __declspec (align (16))
 *  The MSVC Processor Pack Upgrade is required for memory alignement in MS
 *  and the new call is _mm_malloc(sz,alignment) instead of malloc().
 *  Remember to use _mm_free(); to free the code.  Reference:
 *  http://cfxweb.net/modules.php?name=News&file=article&sid=1316
 *
 *  The challenge is now on for the PowerPC gurus to adapt this code to use
 *  the PowerPC's Altivec SIMD engine to achieve the same performance
 *  increases.  PA-RISC has the MAX extensions, the Alpha has MVI, the SGI
 *  has MDMX, and the UltraSPARC has VIS.  Good luck guys!  :-)
 *
 *  P.S.        Sorry MEJ.  :-/
 *
 *