`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    20:39:35 09/03/2006 
// Design Name: 
// Module Name:    top 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module top(address, data, r_w, clock, mem_enable, reset, PC, S, P, A, X, Y);
output [15:0] address;
inout [7:0] data;
output r_w;
input clock;
input reset;
output [15:0] PC;
output [7:0] A, X, Y, S, P;
output mem_enable;

reg [15:0] address;
reg r_w;
reg mem_enable;
wire clock;
wire [7:0] data;
wire reset;

reg [7:0] A,X,Y; // Accumulator, X, Y
reg [7:0] S,P; // Stack pointer, Processor flags
reg [15:0] PC; // Program Counter

reg [7:0] temp_opcode;
reg [7:0] temp_data;
reg [15:0] temp_address;
reg [5:0] temp_state;

`include "load_store.v"
`include "defines.v"

always @(posedge clock)
begin
	if (reset)
		begin
		PC <= 16'h0000;
		temp_state <= 8'h00;
		r_w <= 1'b1;
		end
	else
		begin
		temp_state <= temp_state + 1;
		if(temp_state <= 3)
			begin
			case(temp_state)
				8'h00 :
					begin
					set_address_PC;
					end
				8'h01 :
					begin
					load_opcode;
					end
				8'h02 :
					begin
					PC <= PC + 1;
					end
				8'h03 :
					begin
					end
			endcase
			end
		else
			begin
			case(temp_opcode)
				8'hA9, 8'hA2, 8'hA0: // LDA,LDX,LDY immediate
					begin
					case(temp_state)
						8'h04 :
							set_address_PC;
						8'h05:
							case (temp_opcode)
								8'hA9 : load_data_A;
								8'hA2 : load_data_X;
								8'hA0 : load_data_Y;
							endcase
						8'h06:
							PC <= PC + 1;
						8'h07:
							temp_state <= 8'h00;
					endcase
					end
				8'hA5, 8'hA6, 8'hA4 : // LDA,LDX,LDY zero page
					begin
					case(temp_state)
						8'h04 :
							set_address_PC;
						8'h05:
							load_temp_address_zeropage;
						8'h06:
							PC <= PC + 1;
						//8'h07:
						8'h08:
							set_address_temp;
						8'h09:
							case (temp_opcode)
								8'hA5 : load_data_A;
								8'hA6 : load_data_X;
								8'hA4 : load_data_Y;
							endcase
						//8'h0A:
						8'h0B:
							temp_state <= 8'h00;
					endcase
					end
				8'hAD, 8'hAE, 8'hAC : // LDA,LDX,LDY absolute
					begin
					case(temp_state)
						8'h04 :
							set_address_PC;
						8'h05:
							load_temp_address_lo;
						8'h06:
							PC <= PC + 1;
						//8'h07:
						8'h08:
							set_address_PC;
						8'h09:
							load_temp_address_hi;
						8'h0A:
							PC <= PC + 1;
						//8'h0B:
						8'h0C:
							set_address_temp;
						8'h0D:
							case (temp_opcode)
								8'hA5 : load_data_A;
								8'hA6 : load_data_X;
								8'hA4 : load_data_Y;
							endcase
						//8'h0E:
						8'h0F:
							temp_state <= 8'h00;
					endcase
					end
				default:
					if(temp_state == 8'h07)
						temp_state <= 8'h00; // NOP
			endcase
			end
		end
end
endmodule