diff --git a/src/mesa/drivers/dri/r600/r600_blit.c b/src/mesa/drivers/dri/r600/r600_blit.c
index 244fdc4..e3ee203 100644
--- a/src/mesa/drivers/dri/r600/r600_blit.c
+++ b/src/mesa/drivers/dri/r600/r600_blit.c
@@ -347,7 +347,7 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
     SETfield(cb_color0_info, format, CB_COLOR0_INFO__FORMAT_shift,
              CB_COLOR0_INFO__FORMAT_mask);
     SETfield(cb_color0_info, comp_swap, COMP_SWAP_shift, COMP_SWAP_mask);
-
+    
     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
     R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE + (4 * id), 1);
     R600_OUT_BATCH(cb_color0_base);
@@ -360,8 +360,8 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
     if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
 	(context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
 	    BEGIN_BATCH_NO_AUTOSTATE(2);
-	    R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
-	    R600_OUT_BATCH((2 << id));
+	    R600_OUT_BATCHX2(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0),
+	    /* R600_OUT_BATCH( */ (2 << id)); 
 	    END_BATCH();
     }
 
@@ -369,6 +369,7 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
      * we don't use those this shouldn't cause any issue and we
      * then have a valid cmd stream
      */
+
     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
     R600_OUT_BATCH_REGSEQ(CB_COLOR0_TILE + (4 * id), 1);
     R600_OUT_BATCH(cb_color0_base);
@@ -377,6 +378,7 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
 			 0,
 			 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
     END_BATCH();
+
     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
     R600_OUT_BATCH_REGSEQ(CB_COLOR0_FRAG + (4 * id), 1);
     R600_OUT_BATCH(cb_color0_base);
@@ -462,6 +464,7 @@ set_shaders(context_t *context)
     R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_FS, sq_pgm_cf_offset_fs);
     END_BATCH();
 
+
     /* VS */
     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
     R600_OUT_BATCH_REGSEQ(SQ_PGM_START_VS, 1);
@@ -477,6 +480,7 @@ set_shaders(context_t *context)
     R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_VS, sq_pgm_cf_offset_vs);
     END_BATCH();
 
+
     /* PS */
     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
     R600_OUT_BATCH_REGSEQ(SQ_PGM_START_PS, 1);
@@ -513,13 +517,13 @@ set_vtx_resource(context_t *context)
     BATCH_LOCALS(&context->radeon);
 
     BEGIN_BATCH_NO_AUTOSTATE(6);
-    R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
-    R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
-    R600_OUT_BATCH(0);
+    R600_OUT_BATCHX6(CP_PACKET3(R600_IT_SET_CTL_CONST, 1),
+    /* R600_OUT_BATCH( */ mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX,
+    /* R600_OUT_BATCH( */ 0,
 
-    R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
-    R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX);
-    R600_OUT_BATCH(0);
+    /* R600_OUT_BATCH( */ CP_PACKET3(R600_IT_SET_CTL_CONST, 1),
+    /* R600_OUT_BATCH( */ mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX,
+    /* R600_OUT_BATCH( */ 0);
     END_BATCH();
     COMMIT_BATCH();
 
@@ -534,15 +538,15 @@ set_vtx_resource(context_t *context)
 
     BEGIN_BATCH_NO_AUTOSTATE(9 + 2);
 
-    R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
-    R600_OUT_BATCH(SQ_FETCH_RESOURCE_VS_OFFSET * FETCH_RESOURCE_STRIDE);
-    R600_OUT_BATCH(0);
-    R600_OUT_BATCH(48 - 1);
-    R600_OUT_BATCH(16 << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift);
-    R600_OUT_BATCH(1 << MEM_REQUEST_SIZE_shift);
-    R600_OUT_BATCH(0);
-    R600_OUT_BATCH(0);
-    R600_OUT_BATCH(SQ_TEX_VTX_VALID_BUFFER << SQ_TEX_RESOURCE_WORD6_0__TYPE_shift);
+    R600_OUT_BATCHX9(CP_PACKET3(R600_IT_SET_RESOURCE, 7),
+    /* R600_OUT_BATCH( */ SQ_FETCH_RESOURCE_VS_OFFSET * FETCH_RESOURCE_STRIDE,
+    /* R600_OUT_BATCH( */ 0,
+    /* R600_OUT_BATCH( */ 48 - 1,
+    /* R600_OUT_BATCH( */ 16 << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift,
+    /* R600_OUT_BATCH( */ 1 << MEM_REQUEST_SIZE_shift,
+    /* R600_OUT_BATCH( */ 0,
+    /* R600_OUT_BATCH( */ 0,
+    /* R600_OUT_BATCH( */ SQ_TEX_VTX_VALID_BUFFER << SQ_TEX_RESOURCE_WORD6_0__TYPE_shift);
     R600_OUT_BATCH_RELOC(SQ_VTX_CONSTANT_WORD0_0,
                          bo,
                          SQ_VTX_CONSTANT_WORD0_0,
@@ -1102,16 +1106,16 @@ set_tex_resource(context_t * context,
 		 0, TC_ACTION_ENA_bit);
 
     BEGIN_BATCH_NO_AUTOSTATE(9 + 4);
-    R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
-    R600_OUT_BATCH(0 * 7);
-
-    R600_OUT_BATCH(sq_tex_resource0);
-    R600_OUT_BATCH(sq_tex_resource1);
-    R600_OUT_BATCH(sq_tex_resource2);
-    R600_OUT_BATCH(0); //SQ_TEX_RESOURCE3
-    R600_OUT_BATCH(sq_tex_resource4);
-    R600_OUT_BATCH(0); //SQ_TEX_RESOURCE5
-    R600_OUT_BATCH(sq_tex_resource6);
+    R600_OUT_BATCHX9(CP_PACKET3(R600_IT_SET_RESOURCE, 7),
+    /* R600_OUT_BATCH( */ 0 * 7,
+
+    /* R600_OUT_BATCH( */ sq_tex_resource0,
+    /* R600_OUT_BATCH( */ sq_tex_resource1,
+    /* R600_OUT_BATCH( */ sq_tex_resource2,
+    /* R600_OUT_BATCH( */ 0, //SQ_TEX_RESOURCE3
+    /* R600_OUT_BATCH( */ sq_tex_resource4,
+    /* R600_OUT_BATCH( */ 0, //SQ_TEX_RESOURCE5
+    /* R600_OUT_BATCH( */ sq_tex_resource6);
     R600_OUT_BATCH_RELOC(0,
 		     bo,
 		     0,
@@ -1135,11 +1139,11 @@ set_tex_sampler(context_t * context)
     BATCH_LOCALS(&context->radeon);
 
     BEGIN_BATCH_NO_AUTOSTATE(5);
-    R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
-    R600_OUT_BATCH(i * 3);
-    R600_OUT_BATCH(sq_tex_sampler_word0);
-    R600_OUT_BATCH(sq_tex_sampler_word1);
-    R600_OUT_BATCH(sq_tex_sampler_word2);
+    R600_OUT_BATCHX5(CP_PACKET3(R600_IT_SET_SAMPLER, 3),
+    /* R600_OUT_BATCH( */ i * 3,
+    /* R600_OUT_BATCH( */ sq_tex_sampler_word0,
+    /* R600_OUT_BATCH( */ sq_tex_sampler_word1,
+    /* R600_OUT_BATCH( */ sq_tex_sampler_word2);
     END_BATCH();
 
 }
@@ -1151,22 +1155,22 @@ set_scissors(context_t *context, int x1, int y1, int x2, int y2)
 
     BEGIN_BATCH_NO_AUTOSTATE(17);
     R600_OUT_BATCH_REGSEQ(PA_SC_SCREEN_SCISSOR_TL, 2);
-    R600_OUT_BATCH((x1 << 0) | (y1 << 16));
-    R600_OUT_BATCH((x2 << 0) | (y2 << 16));
+    R600_OUT_BATCHX2((x1 << 0) | (y1 << 16),
+    /* R600_OUT_BATCH( */ (x2 << 0) | (y2 << 16));
 
     R600_OUT_BATCH_REGSEQ(PA_SC_WINDOW_OFFSET, 3);
-    R600_OUT_BATCH(0); //PA_SC_WINDOW_OFFSET
-    R600_OUT_BATCH((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit)); //PA_SC_WINDOW_SCISSOR_TL
-    R600_OUT_BATCH((x2 << 0) | (y2 << 16));
+    R600_OUT_BATCHX3(0, //PA_SC_WINDOW_OFFSET
+    /* R600_OUT_BATCH( */ (x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit), //PA_SC_WINDOW_SCISSOR_TL
+    /* R600_OUT_BATCH( */ (x2 << 0) | (y2 << 16));
 
     R600_OUT_BATCH_REGSEQ(PA_SC_GENERIC_SCISSOR_TL, 2);
-    R600_OUT_BATCH((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit));
-    R600_OUT_BATCH((x2 << 0) | (y2 << 16));
+    R600_OUT_BATCHX2((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit),
+    /* R600_OUT_BATCH( */ (x2 << 0) | (y2 << 16));
 
     /* XXX 16 of these PA_SC_VPORT_SCISSOR_0_TL_num ... */
     R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_SCISSOR_0_TL, 2 );
-    R600_OUT_BATCH((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit));
-    R600_OUT_BATCH((x2 << 0) | (y2 << 16));
+    R600_OUT_BATCHX2((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit),
+    /* R600_OUT_BATCH( */ (x2 << 0) | (y2 << 16));
     END_BATCH();
 
     COMMIT_BATCH();
@@ -1181,20 +1185,20 @@ set_vb_data(context_t * context, int src_x, int src_y, int dst_x, int dst_y,
     radeon_bo_map(context->blit_bo, 1);
     vb = context->blit_bo->ptr;
 
-    vb[0] = (float)(dst_x);
+    vb[0] = vb[4] = (float)(dst_x);
     vb[1] = (float)(dst_y);
-    vb[2] = (float)(src_x);
+    vb[2] = vb[6] = (float)(src_x);
     vb[3] = (flip_y) ? (float)(src_h - src_y) : (float)src_y;
 
-    vb[4] = (float)(dst_x);
-    vb[5] = (float)(dst_y + h);
-    vb[6] = (float)(src_x);
-    vb[7] = (flip_y) ? (float)(src_h - (src_y + h)) : (float)(src_y + h);
+/*    vb[4] = (float)(dst_x); */
+    vb[5] = vb[9] = (float)(dst_y + h);
+/*    vb[6] = (float)(src_x); */
+    vb[7] = vb[11] = (flip_y) ? (float)(src_h - (src_y + h)) : (float)(src_y + h);
 
     vb[8] = (float)(dst_x + w);
-    vb[9] = (float)(dst_y + h);
+/*    vb[9] = (float)(dst_y + h); */
     vb[10] = (float)(src_x + w);
-    vb[11] = (flip_y) ? (float)(src_h - (src_y + h)) : (float)(src_y + h);
+/*    vb[11] = (flip_y) ? (float)(src_h - (src_y + h)) : (float)(src_y + h); */
 
     radeon_bo_unmap(context->blit_bo);
 
@@ -1221,16 +1225,16 @@ draw_auto(context_t *context)
     BEGIN_BATCH_NO_AUTOSTATE(10);
     // prim
     R600_OUT_BATCH_REGSEQ(VGT_PRIMITIVE_TYPE, 1);
-    R600_OUT_BATCH(vgt_primitive_type);
+    R600_OUT_BATCHX7(vgt_primitive_type,
     // index type
-    R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
-    R600_OUT_BATCH(vgt_index_type);
+    /* R600_OUT_BATCH( */ CP_PACKET3(R600_IT_INDEX_TYPE, 0),
+    /* R600_OUT_BATCH( */ vgt_index_type,
     // num instances
-    R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
-    R600_OUT_BATCH(1);
+    /* R600_OUT_BATCH( */ CP_PACKET3(R600_IT_NUM_INSTANCES, 0),
+    /* R600_OUT_BATCH( */ 1,
     //
-    R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1));
-    R600_OUT_BATCH(vgt_num_indices);
+    /* R600_OUT_BATCH( */ CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1),
+    /* R600_OUT_BATCH( */ vgt_num_indices);
     R600_OUT_BATCH(vgt_draw_initiator);
 
     END_BATCH();
@@ -1445,12 +1449,12 @@ set_default_state(context_t *context)
 
     BEGIN_BATCH_NO_AUTOSTATE(117);
     R600_OUT_BATCH_REGSEQ(SQ_CONFIG, 6);
-    R600_OUT_BATCH(sq_config);
-    R600_OUT_BATCH(sq_gpr_resource_mgmt_1);
-    R600_OUT_BATCH(sq_gpr_resource_mgmt_2);
-    R600_OUT_BATCH(sq_thread_resource_mgmt);
-    R600_OUT_BATCH(sq_stack_resource_mgmt_1);
-    R600_OUT_BATCH(sq_stack_resource_mgmt_2);
+    R600_OUT_BATCHX6(sq_config,
+    /* R600_OUT_BATCH( */ sq_gpr_resource_mgmt_1,
+    /* R600_OUT_BATCH( */ sq_gpr_resource_mgmt_2,
+    /* R600_OUT_BATCH( */ sq_thread_resource_mgmt,
+    /* R600_OUT_BATCH( */ sq_stack_resource_mgmt_1,
+    /* R600_OUT_BATCH( */ sq_stack_resource_mgmt_2);
 
     R600_OUT_BATCH_REGVAL(TA_CNTL_AUX, ta_cntl_aux);
     R600_OUT_BATCH_REGVAL(VC_ENHANCE, 0);
@@ -1459,15 +1463,15 @@ set_default_state(context_t *context)
     R600_OUT_BATCH_REGVAL(DB_WATERMARKS, db_watermarks);
 
     R600_OUT_BATCH_REGSEQ(SQ_ESGS_RING_ITEMSIZE, 9);
-    R600_OUT_BATCH(0);
-    R600_OUT_BATCH(0);
-    R600_OUT_BATCH(0);
-    R600_OUT_BATCH(0);
-    R600_OUT_BATCH(0);
-    R600_OUT_BATCH(0);
-    R600_OUT_BATCH(0);
-    R600_OUT_BATCH(0);
-    R600_OUT_BATCH(0);
+    R600_OUT_BATCHX9(0,
+    /* R600_OUT_BATCH( */ 0,
+    /* R600_OUT_BATCH( */ 0,
+    /* R600_OUT_BATCH( */ 0,
+    /* R600_OUT_BATCH( */ 0,
+    /* R600_OUT_BATCH( */ 0,
+    /* R600_OUT_BATCH( */ 0,
+    /* R600_OUT_BATCH( */ 0,
+    /* R600_OUT_BATCH( */ 0);
 
     R600_OUT_BATCH_REGVAL(CB_CLRCMP_CONTROL,
                          (CLRCMP_SEL_SRC << CLRCMP_FCN_SEL_shift));
@@ -1491,24 +1495,24 @@ set_default_state(context_t *context)
         (X_1_256TH << QUANT_MODE_shift));
 
     R600_OUT_BATCH_REGSEQ(VGT_MAX_VTX_INDX, 4);
-    R600_OUT_BATCH(2048);
-    R600_OUT_BATCH(0);
-    R600_OUT_BATCH(0);
-    R600_OUT_BATCH(0);
+    R600_OUT_BATCHX4(2048,
+    /* R600_OUT_BATCH( */ 0,
+    /* R600_OUT_BATCH( */ 0,
+    /* R600_OUT_BATCH( */ 0);
 
     R600_OUT_BATCH_REGSEQ(VGT_OUTPUT_PATH_CNTL, 13);
-    R600_OUT_BATCH(0);
-    R600_OUT_BATCH(0);
-    R600_OUT_BATCH(0);
-    R600_OUT_BATCH(0);
-    R600_OUT_BATCH(0);
-    R600_OUT_BATCH(0);
-    R600_OUT_BATCH(0);
-    R600_OUT_BATCH(0);
-    R600_OUT_BATCH(0);
-    R600_OUT_BATCH(0);
-    R600_OUT_BATCH(0);
-    R600_OUT_BATCH(0);
+    R600_OUT_BATCHX12(0,
+    /* R600_OUT_BATCH( */ 0,
+    /* R600_OUT_BATCH( */ 0,
+    /* R600_OUT_BATCH( */ 0,
+    /* R600_OUT_BATCH( */ 0,
+    /* R600_OUT_BATCH( */ 0,
+    /* R600_OUT_BATCH( */ 0,
+    /* R600_OUT_BATCH( */ 0,
+    /* R600_OUT_BATCH( */ 0,
+    /* R600_OUT_BATCH( */ 0,
+    /* R600_OUT_BATCH( */ 0,
+    /* R600_OUT_BATCH( */ 0);
     R600_OUT_BATCH(0);
 
     R600_OUT_BATCH_REGVAL(VGT_PRIMITIVEID_EN, 0);
@@ -1517,9 +1521,9 @@ set_default_state(context_t *context)
     R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_1, 0);
 
     R600_OUT_BATCH_REGSEQ(VGT_STRMOUT_EN, 3);
-    R600_OUT_BATCH(0);
-    R600_OUT_BATCH(0);
-    R600_OUT_BATCH(0);
+    R600_OUT_BATCHX3(0,
+    /* R600_OUT_BATCH( */ 0,
+    /* R600_OUT_BATCH( */ 0);
 
     R600_OUT_BATCH_REGVAL(VGT_STRMOUT_BUFFER_EN, 0);
 
diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.h b/src/mesa/drivers/dri/r600/r600_cmdbuf.h
index dff0009..1a4decb 100644
--- a/src/mesa/drivers/dri/r600/r600_cmdbuf.h
+++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.h
@@ -129,6 +129,79 @@ do {							\
 } while(0)
 
 /**
+ * Write two dwords to the command buffer.
+ */
+#define R600_OUT_BATCHX2(data1,data2)                           \
+do {                                                    \
+        radeon_cs_write_two_dwords(b_l_rmesa->cmdbuf.cs, data1, data2); \
+} while(0)
+
+/**
+ * Write three dwords to the command buffer.
+ */
+#define R600_OUT_BATCHX3(data1, data2, data3)                           \
+do {                                                    \
+        radeon_cs_write_three_dwords(b_l_rmesa->cmdbuf.cs, data1, data2, data3);        \
+} while(0)
+
+/**
+ * Write four dwords to the command buffer.
+ */
+#define R600_OUT_BATCHX4(data1, data2, data3, data4)                            \
+do {                                                    \
+        radeon_cs_write_four_dwords(b_l_rmesa->cmdbuf.cs, data1, data2, data3, data4 ); \
+} while(0)
+
+/**
+ * Write five dwords to the command buffer.
+ */
+#define R600_OUT_BATCHX5(data1, data2, data3, data4, data5)                             \
+do {                                                    \
+        radeon_cs_write_five_dwords(b_l_rmesa->cmdbuf.cs, data1, data2, data3, data4, data5 );  \
+} while(0)
+
+/**
+ * Write six dwords to the command buffer.
+ */
+#define R600_OUT_BATCHX6(data1, data2, data3, data4, data5, data6)                              \
+do {                                                    \
+        radeon_cs_write_six_dwords(b_l_rmesa->cmdbuf.cs, data1, data2, data3, data4, data5, data6  );   \
+} while(0)
+
+/**
+ * Write seven dwords to the command buffer.
+ */
+#define R600_OUT_BATCHX7(data1, data2, data3, data4, data5, data6, data7)                               \
+do {                                                    \
+        radeon_cs_write_seven_dwords(b_l_rmesa->cmdbuf.cs, data1, data2, data3, data4, data5, data6, data7);    \
+} while(0)
+
+/**
+ * Write nine dwords to the command buffer.
+ */
+#define R600_OUT_BATCHX9(data1, data2, data3, data4, data5, data6, data7, data8, data9)                         \
+do {                                                    \
+        radeon_cs_write_nine_dwords(b_l_rmesa->cmdbuf.cs, data1, data2, data3, data4, data5, data6, data7, data8, data9);       \
+} while(0)
+
+/**
+ * Write ten dwords to the command buffer.
+ */
+#define R600_OUT_BATCHX10(data1, data2, data3, data4, data5, data6, data7, data8, data9, data10)                                \
+do {                                                    \
+        radeon_cs_write_ten_dwords(b_l_rmesa->cmdbuf.cs, data1, data2, data3, data4, data5, data6, data7, data8, data9, data10);        \
+} while(0)
+
+/**
+ * Write twelve dwords to the command buffer.
+ */
+#define R600_OUT_BATCHX12(data1, data2, data3, data4, data5, data6, data7, data8, data9, data10, data11, data12)                                \
+do {                                                    \
+        radeon_cs_write_twelve_dwords(b_l_rmesa->cmdbuf.cs, data1, data2, data3, data4, data5, data6, data7, data8, data9, data10, data11, data12);     \
+} while(0)
+
+
+/**
  * Write n dwords from ptr to the command buffer.
  */
 #define R600_OUT_BATCH_TABLE(ptr,n)		\
@@ -150,41 +223,77 @@ do {						     \
 	} while(0)
 
 /* R600/R700 */
-#define R600_OUT_BATCH_REGS(reg, num)					\
-do {								\
-	if ((reg) >= R600_SET_CONFIG_REG_OFFSET && (reg) < R600_SET_CONFIG_REG_END) { \
-		R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, (num)));	\
-		R600_OUT_BATCH(((reg) - R600_SET_CONFIG_REG_OFFSET) >> 2);	\
-	} else if ((reg) >= R600_SET_CONTEXT_REG_OFFSET && (reg) < R600_SET_CONTEXT_REG_END) { \
-		R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONTEXT_REG, (num)));	\
-		R600_OUT_BATCH(((reg) - R600_SET_CONTEXT_REG_OFFSET) >> 2);	\
-	} else if ((reg) >= R600_SET_ALU_CONST_OFFSET && (reg) < R600_SET_ALU_CONST_END) { \
-		R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (num)));	\
-		R600_OUT_BATCH(((reg) - R600_SET_ALU_CONST_OFFSET) >> 2);	\
-	} else if ((reg) >= R600_SET_RESOURCE_OFFSET && (reg) < R600_SET_RESOURCE_END) { \
-		R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, (num)));	\
-		R600_OUT_BATCH(((reg) - R600_SET_RESOURCE_OFFSET) >> 2);	\
-	} else if ((reg) >= R600_SET_SAMPLER_OFFSET && (reg) < R600_SET_SAMPLER_END) { \
-		R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, (num)));	\
-		R600_OUT_BATCH(((reg) - R600_SET_SAMPLER_OFFSET) >> 2);	\
-	} else if ((reg) >= R600_SET_CTL_CONST_OFFSET && (reg) < R600_SET_CTL_CONST_END) { \
-		R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, (num)));	\
-		R600_OUT_BATCH(((reg) - R600_SET_CTL_CONST_OFFSET) >> 2);	\
-	} else if ((reg) >= R600_SET_LOOP_CONST_OFFSET && (reg) < R600_SET_LOOP_CONST_END) { \
-		R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_LOOP_CONST, (num)));	\
-		R600_OUT_BATCH(((reg) - R600_SET_LOOP_CONST_OFFSET) >> 2);	\
-	} else if ((reg) >= R600_SET_BOOL_CONST_OFFSET && (reg) < R600_SET_BOOL_CONST_END) { \
-		R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_BOOL_CONST, (num)));	\
-		R600_OUT_BATCH(((reg) - R600_SET_BOOL_CONST_OFFSET) >> 2);	\
-	} else {							\
-		R600_OUT_BATCH(CP_PACKET0((reg), (num))); \
-	}								\
+#define R600_OUT_BATCH_REGS(reg, num)                                   \
+do {                                                            \
+        if ((reg) >= R600_SET_CONFIG_REG_OFFSET && (reg) < R600_SET_CONFIG_REG_END) { \
+                R600_OUT_BATCHX2(CP_PACKET3(R600_IT_SET_CONFIG_REG, (num)),     \
+                /*R600_OUT_BATCH( */((reg) - R600_SET_CONFIG_REG_OFFSET) >> 2); \
+        } else if ((reg) >= R600_SET_CONTEXT_REG_OFFSET && (reg) < R600_SET_CONTEXT_REG_END) { \
+                R600_OUT_BATCHX2(CP_PACKET3(R600_IT_SET_CONTEXT_REG, (num)),    \
+                /*R600_OUT_BATCH(*/((reg) - R600_SET_CONTEXT_REG_OFFSET) >> 2); \
+        } else if ((reg) >= R600_SET_ALU_CONST_OFFSET && (reg) < R600_SET_ALU_CONST_END) { \
+                R600_OUT_BATCHX2(CP_PACKET3(R600_IT_SET_ALU_CONST, (num)),      \
+                /*R600_OUT_BATCH(*/((reg) - R600_SET_ALU_CONST_OFFSET) >> 2);   \
+        } else if ((reg) >= R600_SET_RESOURCE_OFFSET && (reg) < R600_SET_RESOURCE_END) { \
+                R600_OUT_BATCHX2(CP_PACKET3(R600_IT_SET_RESOURCE, (num)),       \
+                /*R600_OUT_BATCH(*/((reg) - R600_SET_RESOURCE_OFFSET) >> 2);    \
+        } else if ((reg) >= R600_SET_SAMPLER_OFFSET && (reg) < R600_SET_SAMPLER_END) { \
+                R600_OUT_BATCHX2(CP_PACKET3(R600_IT_SET_SAMPLER, (num)),        \
+                /*R600_OUT_BATCH(*/((reg) - R600_SET_SAMPLER_OFFSET) >> 2);     \
+        } else if ((reg) >= R600_SET_CTL_CONST_OFFSET && (reg) < R600_SET_CTL_CONST_END) { \
+                R600_OUT_BATCHX2(CP_PACKET3(R600_IT_SET_CTL_CONST, (num)),      \
+                /*R600_OUT_BATCH(*/((reg) - R600_SET_CTL_CONST_OFFSET) >> 2);   \
+        } else if ((reg) >= R600_SET_LOOP_CONST_OFFSET && (reg) < R600_SET_LOOP_CONST_END) { \
+                R600_OUT_BATCHX2(CP_PACKET3(R600_IT_SET_LOOP_CONST, (num)),     \
+                /*R600_OUT_BATCH(*/((reg) - R600_SET_LOOP_CONST_OFFSET) >> 2);  \
+        } else if ((reg) >= R600_SET_BOOL_CONST_OFFSET && (reg) < R600_SET_BOOL_CONST_END) { \
+                R600_OUT_BATCHX2(CP_PACKET3(R600_IT_SET_BOOL_CONST, (num)),     \
+                /*R600_OUT_BATCH(*/((reg) - R600_SET_BOOL_CONST_OFFSET) >> 2);  \
+        } else {                                                        \
+                R600_OUT_BATCH(CP_PACKET0((reg), (num))); \
+        }                                                               \
 } while (0)
 
 /** Single register write to command buffer; requires 3 dwords for most things. */
-#define R600_OUT_BATCH_REGVAL(reg, val)		\
-	R600_OUT_BATCH_REGS((reg), 1);		\
-	R600_OUT_BATCH((val))
+#define R600_OUT_BATCH_REGVAL(reg, val)         \
+do {                                                            \
+        if ((reg) >= R600_SET_CONFIG_REG_OFFSET && (reg) < R600_SET_CONFIG_REG_END) { \
+                R600_OUT_BATCHX3(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1), \
+                /*R600_OUT_BATCH( */((reg) - R600_SET_CONFIG_REG_OFFSET) >> 2,  \
+                /*R600_OUT_BATCH(*/ val);       \
+        } else if ((reg) >= R600_SET_CONTEXT_REG_OFFSET && (reg) < R600_SET_CONTEXT_REG_END) { \
+                R600_OUT_BATCHX3(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1),        \
+                /*R600_OUT_BATCH(*/((reg) - R600_SET_CONTEXT_REG_OFFSET) >> 2,  \
+                /*R600_OUT_BATCH(*/ val);       \
+        } else if ((reg) >= R600_SET_ALU_CONST_OFFSET && (reg) < R600_SET_ALU_CONST_END) { \
+                R600_OUT_BATCHX3(CP_PACKET3(R600_IT_SET_ALU_CONST, 1),  \
+                /*R600_OUT_BATCH(*/((reg) - R600_SET_ALU_CONST_OFFSET) >> 2,    \
+                /*R600_OUT_BATCH(*/ val);       \
+        } else if ((reg) >= R600_SET_RESOURCE_OFFSET && (reg) < R600_SET_RESOURCE_END) { \
+                R600_OUT_BATCHX3(CP_PACKET3(R600_IT_SET_RESOURCE, 1),   \
+                /*R600_OUT_BATCH(*/((reg) - R600_SET_RESOURCE_OFFSET) >> 2,     \
+                /*R600_OUT_BATCH(*/ val);       \
+        } else if ((reg) >= R600_SET_SAMPLER_OFFSET && (reg) < R600_SET_SAMPLER_END) { \
+                R600_OUT_BATCHX3(CP_PACKET3(R600_IT_SET_SAMPLER, 1),    \
+                /*R600_OUT_BATCH(*/((reg) - R600_SET_SAMPLER_OFFSET) >> 2,      \
+                /*R600_OUT_BATCH(*/ val);       \
+        } else if ((reg) >= R600_SET_CTL_CONST_OFFSET && (reg) < R600_SET_CTL_CONST_END) { \
+                R600_OUT_BATCHX3(CP_PACKET3(R600_IT_SET_CTL_CONST, 1),  \
+                /*R600_OUT_BATCH(*/((reg) - R600_SET_CTL_CONST_OFFSET) >> 2,    \
+                /*R600_OUT_BATCH(*/ val);       \
+        } else if ((reg) >= R600_SET_LOOP_CONST_OFFSET && (reg) < R600_SET_LOOP_CONST_END) { \
+                R600_OUT_BATCHX3(CP_PACKET3(R600_IT_SET_LOOP_CONST, 1), \
+                /*R600_OUT_BATCH(*/((reg) - R600_SET_LOOP_CONST_OFFSET) >> 2,   \
+                /*R600_OUT_BATCH(*/ val);       \
+        } else if ((reg) >= R600_SET_BOOL_CONST_OFFSET && (reg) < R600_SET_BOOL_CONST_END) { \
+                R600_OUT_BATCHX3(CP_PACKET3(R600_IT_SET_BOOL_CONST, 1), \
+                /*R600_OUT_BATCH(*/((reg) - R600_SET_BOOL_CONST_OFFSET) >> 2,   \
+                /*R600_OUT_BATCH(*/ val);       \
+        } else {                                                        \
+                R600_OUT_BATCHX2(CP_PACKET0((reg), (1)), \
+                /*R600_OUT_BATCH(*/ val);       \
+        }                                                               \
+} while (0)
 
 /** Continuous register range write to command buffer; requires 1 dword,
  * expects count dwords afterwards for register contents. */
diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c
index fddac2f..cb61e22 100644
--- a/src/mesa/drivers/dri/r600/r600_context.c
+++ b/src/mesa/drivers/dri/r600/r600_context.c
@@ -218,10 +218,10 @@ static void r600_emit_query_finish(radeonContextPtr radeon)
 	struct radeon_query_object *query = radeon->query.current;
 
 	BEGIN_BATCH_NO_AUTOSTATE(4 + 2);
-	R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2));
-	R600_OUT_BATCH(ZPASS_DONE);
-	R600_OUT_BATCH(query->curr_offset + 8); /* hw writes qwords */
-	R600_OUT_BATCH(0x00000000);
+	R600_OUT_BATCHX4(CP_PACKET3(R600_IT_EVENT_WRITE, 2),
+	/* R600_OUT_BATCH( */ ZPASS_DONE,
+	/* R600_OUT_BATCH( */ query->curr_offset + 8, /* hw writes qwords */
+	/* R600_OUT_BATCH( */ 0x00000000);
 	R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0);
 	END_BATCH();
 	assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index 63614b1..740f2ad 100644
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -79,13 +79,13 @@ static void r700SendTexState(GLcontext *ctx, struct radeon_state_atom *atom)
 					    R600_OUT_BATCH(i * 7);
                     }
 
-					R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0);
-					R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1);
-					R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE2);
-					R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE3);
-					R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4);
-					R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5);
-					R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6);
+					R600_OUT_BATCHX7(r700->textures[i]->SQ_TEX_RESOURCE0,
+					/* R600_OUT_BATCH( */ r700->textures[i]->SQ_TEX_RESOURCE1,
+					/* R600_OUT_BATCH( */ r700->textures[i]->SQ_TEX_RESOURCE2,
+					/* R600_OUT_BATCH( */ r700->textures[i]->SQ_TEX_RESOURCE3,
+					/* R600_OUT_BATCH( */ r700->textures[i]->SQ_TEX_RESOURCE4,
+					/* R600_OUT_BATCH( */ r700->textures[i]->SQ_TEX_RESOURCE5,
+					/* R600_OUT_BATCH( */ r700->textures[i]->SQ_TEX_RESOURCE6);
 					R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2,
 							     bo,
 							     r700->textures[i]->SQ_TEX_RESOURCE2,
@@ -131,9 +131,9 @@ static void r700SendTexSamplerState(GLcontext *ctx, struct radeon_state_atom *at
 				    R600_OUT_BATCH(i * 3);
                 }
 
-				R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER0);
-				R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER1);
-				R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER2);
+				R600_OUT_BATCHX3(r700->textures[i]->SQ_TEX_SAMPLER0,
+				/* R600_OUT_BATCH( */ r700->textures[i]->SQ_TEX_SAMPLER1,
+				/* R600_OUT_BATCH( */ r700->textures[i]->SQ_TEX_SAMPLER2);
 				END_BATCH();
 				COMMIT_BATCH();
 			}
@@ -155,10 +155,10 @@ static void r700SendTexBorderColorState(GLcontext *ctx, struct radeon_state_atom
 			if (t) {
 				BEGIN_BATCH_NO_AUTOSTATE(2 + 4);
 				R600_OUT_BATCH_REGSEQ((TD_PS_SAMPLER0_BORDER_RED + (i * 16)), 4);
-				R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_RED);
-				R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN);
-				R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE);
-				R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA);
+				R600_OUT_BATCHX4(r700->textures[i]->TD_PS_SAMPLER0_BORDER_RED,
+				/* R600_OUT_BATCH( */ r700->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN,
+				/* R600_OUT_BATCH( */ r700->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE,
+				/* R600_OUT_BATCH( */ r700->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA);
 				END_BATCH();
 				COMMIT_BATCH();
 			}
@@ -236,15 +236,15 @@ static void r700SetupVTXConstants(GLcontext  * ctx,
 
     BEGIN_BATCH_NO_AUTOSTATE(9 + 2);
 
-    R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
-    R600_OUT_BATCH((pStreamDesc->element + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE);
-    R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD0_0);
-    R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0);
-    R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0);
-    R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0);
-    R600_OUT_BATCH(0);
-    R600_OUT_BATCH(0);
-    R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD6_0);
+    R600_OUT_BATCHX9(CP_PACKET3(R600_IT_SET_RESOURCE, 7),
+    /* R600_OUT_BATCH( */ (pStreamDesc->element + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE,
+    /* R600_OUT_BATCH( */ uSQ_VTX_CONSTANT_WORD0_0,
+    /* R600_OUT_BATCH( */ uSQ_VTX_CONSTANT_WORD1_0,
+    /* R600_OUT_BATCH( */ uSQ_VTX_CONSTANT_WORD2_0,
+    /* R600_OUT_BATCH( */ uSQ_VTX_CONSTANT_WORD3_0,
+    /* R600_OUT_BATCH( */ 0,
+    /* R600_OUT_BATCH( */ 0,
+    /* R600_OUT_BATCH( */ uSQ_VTX_CONSTANT_WORD6_0);
     R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0,
                          paos->bo,
                          uSQ_VTX_CONSTANT_WORD0_0,
@@ -266,13 +266,13 @@ static void r700SendVTXState(GLcontext *ctx, struct radeon_state_atom *atom)
 	    return;
 
     BEGIN_BATCH_NO_AUTOSTATE(6);
-    R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
-    R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
-    R600_OUT_BATCH(0);
+    R600_OUT_BATCHX6(CP_PACKET3(R600_IT_SET_CTL_CONST, 1),
+    /* R600_OUT_BATCH( */ mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX,
+    /* R600_OUT_BATCH( */ 0,
 
-    R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
-    R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX);
-    R600_OUT_BATCH(0);
+    /* R600_OUT_BATCH( */ CP_PACKET3(R600_IT_SET_CTL_CONST, 1),
+    /* R600_OUT_BATCH( */ mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX,
+    /* R600_OUT_BATCH( */ 0);
     END_BATCH();
     COMMIT_BATCH();
 
@@ -390,11 +390,11 @@ static void r700SendDepthTargetState(GLcontext *ctx, struct radeon_state_atom *a
 
         BEGIN_BATCH_NO_AUTOSTATE(8 + 2);
 	R600_OUT_BATCH_REGSEQ(DB_DEPTH_SIZE, 2);
-	R600_OUT_BATCH(r700->DB_DEPTH_SIZE.u32All);
-	R600_OUT_BATCH(r700->DB_DEPTH_VIEW.u32All);
+	R600_OUT_BATCHX2(r700->DB_DEPTH_SIZE.u32All,
+	/* R600_OUT_BATCH( */ r700->DB_DEPTH_VIEW.u32All);
 	R600_OUT_BATCH_REGSEQ(DB_DEPTH_BASE, 2);
-	R600_OUT_BATCH(r700->DB_DEPTH_BASE.u32All);
-	R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All);
+	R600_OUT_BATCHX2(r700->DB_DEPTH_BASE.u32All,
+	/* R600_OUT_BATCH( */ r700->DB_DEPTH_INFO.u32All);
 	R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All,
 			     rrb->bo,
 			     r700->DB_DEPTH_BASE.u32All,
@@ -404,8 +404,8 @@ static void r700SendDepthTargetState(GLcontext *ctx, struct radeon_state_atom *a
 	if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
 	    (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
 		BEGIN_BATCH_NO_AUTOSTATE(2);
-		R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
-		R600_OUT_BATCH(1 << 0);
+		R600_OUT_BATCHX2(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0),
+		/* R600_OUT_BATCH( */ 1 << 0);
 		END_BATCH();
 	}
 
@@ -447,8 +447,8 @@ static void r700SendRenderTargetState(GLcontext *ctx, struct radeon_state_atom *
 	if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
 	    (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
 		BEGIN_BATCH_NO_AUTOSTATE(2);
-		R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
-		R600_OUT_BATCH((2 << id));
+		R600_OUT_BATCHX2(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0),
+		/* R600_OUT_BATCH( */ (2 << id));
 		END_BATCH();
 	}
 	/* Set CMASK & TILE buffer to the offset of color buffer as
@@ -616,18 +616,18 @@ static void r700SendViewportState(GLcontext *ctx, struct radeon_state_atom *atom
 
         BEGIN_BATCH_NO_AUTOSTATE(16);
 	R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_SCISSOR_0_TL + (8 * id), 2);
-	R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All);
-	R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All);
+	R600_OUT_BATCHX2(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All,
+	/* R600_OUT_BATCH( */ r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All);
 	R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_ZMIN_0 + (8 * id), 2);
-	R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All);
-	R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All);
+	R600_OUT_BATCHX2(r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All,
+	/* R600_OUT_BATCH( */ r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All);
 	R600_OUT_BATCH_REGSEQ(PA_CL_VPORT_XSCALE_0 + (24 * id), 6);
-	R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_XSCALE.u32All);
-	R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_XOFFSET.u32All);
-	R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_YSCALE.u32All);
-	R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_YOFFSET.u32All);
-	R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_ZSCALE.u32All);
-	R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_ZOFFSET.u32All);
+	R600_OUT_BATCHX6(r700->viewport[id].PA_CL_VPORT_XSCALE.u32All,
+	/* R600_OUT_BATCH( */ r700->viewport[id].PA_CL_VPORT_XOFFSET.u32All,
+	/* R600_OUT_BATCH( */ r700->viewport[id].PA_CL_VPORT_YSCALE.u32All,
+	/* R600_OUT_BATCH( */ r700->viewport[id].PA_CL_VPORT_YOFFSET.u32All,
+	/* R600_OUT_BATCH( */ r700->viewport[id].PA_CL_VPORT_ZSCALE.u32All,
+	/* R600_OUT_BATCH( */ r700->viewport[id].PA_CL_VPORT_ZOFFSET.u32All);
         END_BATCH();
 
 	COMMIT_BATCH();
@@ -643,12 +643,12 @@ static void r700SendSQConfig(GLcontext *ctx, struct radeon_state_atom *atom)
 
         BEGIN_BATCH_NO_AUTOSTATE(34);
 	R600_OUT_BATCH_REGSEQ(SQ_CONFIG, 6);
-	R600_OUT_BATCH(r700->sq_config.SQ_CONFIG.u32All);
-	R600_OUT_BATCH(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All);
-	R600_OUT_BATCH(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All);
-	R600_OUT_BATCH(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All);
-	R600_OUT_BATCH(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All);
-	R600_OUT_BATCH(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All);
+	R600_OUT_BATCHX6(r700->sq_config.SQ_CONFIG.u32All,
+	/* R600_OUT_BATCH( */ r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All,
+	/* R600_OUT_BATCH( */ r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All,
+	/* R600_OUT_BATCH( */ r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All,
+	/* R600_OUT_BATCH( */ r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All,
+	/* R600_OUT_BATCH( */ r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All);
 
 	R600_OUT_BATCH_REGVAL(TA_CNTL_AUX, r700->TA_CNTL_AUX.u32All);
 	R600_OUT_BATCH_REGVAL(VC_ENHANCE, r700->VC_ENHANCE.u32All);
@@ -657,15 +657,15 @@ static void r700SendSQConfig(GLcontext *ctx, struct radeon_state_atom *atom)
 	R600_OUT_BATCH_REGVAL(DB_WATERMARKS, r700->DB_WATERMARKS.u32All);
 
 	R600_OUT_BATCH_REGSEQ(SQ_ESGS_RING_ITEMSIZE, 9);
-	R600_OUT_BATCH(r700->SQ_ESGS_RING_ITEMSIZE.u32All);
-	R600_OUT_BATCH(r700->SQ_GSVS_RING_ITEMSIZE.u32All);
-	R600_OUT_BATCH(r700->SQ_ESTMP_RING_ITEMSIZE.u32All);
-	R600_OUT_BATCH(r700->SQ_GSTMP_RING_ITEMSIZE.u32All);
-	R600_OUT_BATCH(r700->SQ_VSTMP_RING_ITEMSIZE.u32All);
-	R600_OUT_BATCH(r700->SQ_PSTMP_RING_ITEMSIZE.u32All);
-	R600_OUT_BATCH(r700->SQ_FBUF_RING_ITEMSIZE.u32All);
-	R600_OUT_BATCH(r700->SQ_REDUC_RING_ITEMSIZE.u32All);
-	R600_OUT_BATCH(r700->SQ_GS_VERT_ITEMSIZE.u32All);
+	R600_OUT_BATCHX9(r700->SQ_ESGS_RING_ITEMSIZE.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_GSVS_RING_ITEMSIZE.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_ESTMP_RING_ITEMSIZE.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_GSTMP_RING_ITEMSIZE.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_VSTMP_RING_ITEMSIZE.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_PSTMP_RING_ITEMSIZE.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_FBUF_RING_ITEMSIZE.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_REDUC_RING_ITEMSIZE.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_GS_VERT_ITEMSIZE.u32All);
         END_BATCH();
 
 	COMMIT_BATCH();
@@ -683,10 +683,10 @@ static void r700SendUCPState(GLcontext *ctx, struct radeon_state_atom *atom)
 		if (r700->ucp[i].enabled) {
 			BEGIN_BATCH_NO_AUTOSTATE(6);
 			R600_OUT_BATCH_REGSEQ(PA_CL_UCP_0_X + (16 * i), 4);
-			R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_X.u32All);
-			R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_Y.u32All);
-			R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_Z.u32All);
-			R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_W.u32All);
+			R600_OUT_BATCHX4(r700->ucp[i].PA_CL_UCP_0_X.u32All,
+			/* R600_OUT_BATCH( */ r700->ucp[i].PA_CL_UCP_0_Y.u32All,
+			/* R600_OUT_BATCH( */ r700->ucp[i].PA_CL_UCP_0_Z.u32All,
+			/* R600_OUT_BATCH( */ r700->ucp[i].PA_CL_UCP_0_W.u32All);
 			END_BATCH();
 			COMMIT_BATCH();
 		}
@@ -704,61 +704,61 @@ static void r700SendSPIState(GLcontext *ctx, struct radeon_state_atom *atom)
 	BEGIN_BATCH_NO_AUTOSTATE(59 + R700_MAX_SHADER_EXPORTS);
 
 	R600_OUT_BATCH_REGSEQ(SQ_VTX_SEMANTIC_0, 32);
-	R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_0.u32All);
-	R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_1.u32All);
-	R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_2.u32All);
-	R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_3.u32All);
-	R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_4.u32All);
-	R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_5.u32All);
-	R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_6.u32All);
-	R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_7.u32All);
-	R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_8.u32All);
-	R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_9.u32All);
-	R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_10.u32All);
-	R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_11.u32All);
-	R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_12.u32All);
-	R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_13.u32All);
-	R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_14.u32All);
-	R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_15.u32All);
-	R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_16.u32All);
-	R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_17.u32All);
-	R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_18.u32All);
-	R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_19.u32All);
-	R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_20.u32All);
-	R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_21.u32All);
-	R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_22.u32All);
-	R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_23.u32All);
-	R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_24.u32All);
-	R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_25.u32All);
-	R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_26.u32All);
-	R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_27.u32All);
-	R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_28.u32All);
-	R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_29.u32All);
-	R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_30.u32All);
-	R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_31.u32All);
+	R600_OUT_BATCHX12(r700->SQ_VTX_SEMANTIC_0.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_VTX_SEMANTIC_1.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_VTX_SEMANTIC_2.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_VTX_SEMANTIC_3.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_VTX_SEMANTIC_4.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_VTX_SEMANTIC_5.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_VTX_SEMANTIC_6.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_VTX_SEMANTIC_7.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_VTX_SEMANTIC_8.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_VTX_SEMANTIC_9.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_VTX_SEMANTIC_10.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_VTX_SEMANTIC_11.u32All);
+	R600_OUT_BATCHX10(r700->SQ_VTX_SEMANTIC_12.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_VTX_SEMANTIC_13.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_VTX_SEMANTIC_14.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_VTX_SEMANTIC_15.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_VTX_SEMANTIC_16.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_VTX_SEMANTIC_17.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_VTX_SEMANTIC_18.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_VTX_SEMANTIC_19.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_VTX_SEMANTIC_20.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_VTX_SEMANTIC_21.u32All);
+	R600_OUT_BATCHX10(  r700->SQ_VTX_SEMANTIC_22.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_VTX_SEMANTIC_23.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_VTX_SEMANTIC_24.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_VTX_SEMANTIC_25.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_VTX_SEMANTIC_26.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_VTX_SEMANTIC_27.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_VTX_SEMANTIC_28.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_VTX_SEMANTIC_29.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_VTX_SEMANTIC_30.u32All,
+	/* R600_OUT_BATCH( */ r700->SQ_VTX_SEMANTIC_31.u32All);
 
 	R600_OUT_BATCH_REGSEQ(SPI_VS_OUT_ID_0, 10);
-	R600_OUT_BATCH(r700->SPI_VS_OUT_ID_0.u32All);
-	R600_OUT_BATCH(r700->SPI_VS_OUT_ID_1.u32All);
-	R600_OUT_BATCH(r700->SPI_VS_OUT_ID_2.u32All);
-	R600_OUT_BATCH(r700->SPI_VS_OUT_ID_3.u32All);
-	R600_OUT_BATCH(r700->SPI_VS_OUT_ID_4.u32All);
-	R600_OUT_BATCH(r700->SPI_VS_OUT_ID_5.u32All);
-	R600_OUT_BATCH(r700->SPI_VS_OUT_ID_6.u32All);
-	R600_OUT_BATCH(r700->SPI_VS_OUT_ID_7.u32All);
-	R600_OUT_BATCH(r700->SPI_VS_OUT_ID_8.u32All);
-	R600_OUT_BATCH(r700->SPI_VS_OUT_ID_9.u32All);
+	R600_OUT_BATCHX10(r700->SPI_VS_OUT_ID_0.u32All,
+	/* R600_OUT_BATCH( */ r700->SPI_VS_OUT_ID_1.u32All,
+	/* R600_OUT_BATCH( */ r700->SPI_VS_OUT_ID_2.u32All,
+	/* R600_OUT_BATCH( */ r700->SPI_VS_OUT_ID_3.u32All,
+	/* R600_OUT_BATCH( */ r700->SPI_VS_OUT_ID_4.u32All,
+	/* R600_OUT_BATCH( */ r700->SPI_VS_OUT_ID_5.u32All,
+	/* R600_OUT_BATCH( */ r700->SPI_VS_OUT_ID_6.u32All,
+	/* R600_OUT_BATCH( */ r700->SPI_VS_OUT_ID_7.u32All,
+	/* R600_OUT_BATCH( */ r700->SPI_VS_OUT_ID_8.u32All,
+	/* R600_OUT_BATCH( */ r700->SPI_VS_OUT_ID_9.u32All);
 
 	R600_OUT_BATCH_REGSEQ(SPI_VS_OUT_CONFIG, 9);
-	R600_OUT_BATCH(r700->SPI_VS_OUT_CONFIG.u32All);
-	R600_OUT_BATCH(r700->SPI_THREAD_GROUPING.u32All);
-	R600_OUT_BATCH(r700->SPI_PS_IN_CONTROL_0.u32All);
-	R600_OUT_BATCH(r700->SPI_PS_IN_CONTROL_1.u32All);
-	R600_OUT_BATCH(r700->SPI_INTERP_CONTROL_0.u32All);
-	R600_OUT_BATCH(r700->SPI_INPUT_Z.u32All);
-	R600_OUT_BATCH(r700->SPI_FOG_CNTL.u32All);
-	R600_OUT_BATCH(r700->SPI_FOG_FUNC_SCALE.u32All);
-	R600_OUT_BATCH(r700->SPI_FOG_FUNC_BIAS.u32All);
+	R600_OUT_BATCHX9(r700->SPI_VS_OUT_CONFIG.u32All,
+	/* R600_OUT_BATCH( */ r700->SPI_THREAD_GROUPING.u32All,
+	/* R600_OUT_BATCH( */ r700->SPI_PS_IN_CONTROL_0.u32All,
+	/* R600_OUT_BATCH( */ r700->SPI_PS_IN_CONTROL_1.u32All,
+	/* R600_OUT_BATCH( */ r700->SPI_INTERP_CONTROL_0.u32All,
+	/* R600_OUT_BATCH( */ r700->SPI_INPUT_Z.u32All,
+	/* R600_OUT_BATCH( */ r700->SPI_FOG_CNTL.u32All,
+	/* R600_OUT_BATCH( */ r700->SPI_FOG_FUNC_SCALE.u32All,
+	/* R600_OUT_BATCH( */ r700->SPI_FOG_FUNC_BIAS.u32All);
 
 	R600_OUT_BATCH_REGSEQ(SPI_PS_INPUT_CNTL_0, R700_MAX_SHADER_EXPORTS);
 	for(ui = 0; ui < R700_MAX_SHADER_EXPORTS; ui++)
@@ -778,24 +778,24 @@ static void r700SendVGTState(GLcontext *ctx, struct radeon_state_atom *atom)
         BEGIN_BATCH_NO_AUTOSTATE(41);
 
 	R600_OUT_BATCH_REGSEQ(VGT_MAX_VTX_INDX, 4);
-	R600_OUT_BATCH(r700->VGT_MAX_VTX_INDX.u32All);
-	R600_OUT_BATCH(r700->VGT_MIN_VTX_INDX.u32All);
-	R600_OUT_BATCH(r700->VGT_INDX_OFFSET.u32All);
-	R600_OUT_BATCH(r700->VGT_MULTI_PRIM_IB_RESET_INDX.u32All);
+	R600_OUT_BATCHX4(r700->VGT_MAX_VTX_INDX.u32All,
+	/* R600_OUT_BATCH( */ r700->VGT_MIN_VTX_INDX.u32All,
+	/* R600_OUT_BATCH( */ r700->VGT_INDX_OFFSET.u32All,
+	/* R600_OUT_BATCH( */ r700->VGT_MULTI_PRIM_IB_RESET_INDX.u32All);
 
 	R600_OUT_BATCH_REGSEQ(VGT_OUTPUT_PATH_CNTL, 13);
-	R600_OUT_BATCH(r700->VGT_OUTPUT_PATH_CNTL.u32All);
-	R600_OUT_BATCH(r700->VGT_HOS_CNTL.u32All);
-	R600_OUT_BATCH(r700->VGT_HOS_MAX_TESS_LEVEL.u32All);
-	R600_OUT_BATCH(r700->VGT_HOS_MIN_TESS_LEVEL.u32All);
-	R600_OUT_BATCH(r700->VGT_HOS_REUSE_DEPTH.u32All);
-	R600_OUT_BATCH(r700->VGT_GROUP_PRIM_TYPE.u32All);
-	R600_OUT_BATCH(r700->VGT_GROUP_FIRST_DECR.u32All);
-	R600_OUT_BATCH(r700->VGT_GROUP_DECR.u32All);
-	R600_OUT_BATCH(r700->VGT_GROUP_VECT_0_CNTL.u32All);
-	R600_OUT_BATCH(r700->VGT_GROUP_VECT_1_CNTL.u32All);
-	R600_OUT_BATCH(r700->VGT_GROUP_VECT_0_FMT_CNTL.u32All);
-	R600_OUT_BATCH(r700->VGT_GROUP_VECT_1_FMT_CNTL.u32All);
+	R600_OUT_BATCHX12(r700->VGT_OUTPUT_PATH_CNTL.u32All,
+	/* R600_OUT_BATCH( */ r700->VGT_HOS_CNTL.u32All,
+	/* R600_OUT_BATCH( */ r700->VGT_HOS_MAX_TESS_LEVEL.u32All,
+	/* R600_OUT_BATCH( */ r700->VGT_HOS_MIN_TESS_LEVEL.u32All,
+	/* R600_OUT_BATCH( */ r700->VGT_HOS_REUSE_DEPTH.u32All,
+	/* R600_OUT_BATCH( */ r700->VGT_GROUP_PRIM_TYPE.u32All,
+	/* R600_OUT_BATCH( */ r700->VGT_GROUP_FIRST_DECR.u32All,
+	/* R600_OUT_BATCH( */ r700->VGT_GROUP_DECR.u32All,
+	/* R600_OUT_BATCH( */ r700->VGT_GROUP_VECT_0_CNTL.u32All,
+	/* R600_OUT_BATCH( */ r700->VGT_GROUP_VECT_1_CNTL.u32All,
+	/* R600_OUT_BATCH( */ r700->VGT_GROUP_VECT_0_FMT_CNTL.u32All,
+	/* R600_OUT_BATCH( */ r700->VGT_GROUP_VECT_1_FMT_CNTL.u32All);
 	R600_OUT_BATCH(r700->VGT_GS_MODE.u32All);
 
 	R600_OUT_BATCH_REGVAL(VGT_PRIMITIVEID_EN, r700->VGT_PRIMITIVEID_EN.u32All);
@@ -804,9 +804,9 @@ static void r700SendVGTState(GLcontext *ctx, struct radeon_state_atom *atom)
 	R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_1, r700->VGT_INSTANCE_STEP_RATE_1.u32All);
 
 	R600_OUT_BATCH_REGSEQ(VGT_STRMOUT_EN, 3);
-	R600_OUT_BATCH(r700->VGT_STRMOUT_EN.u32All);
-	R600_OUT_BATCH(r700->VGT_REUSE_OFF.u32All);
-	R600_OUT_BATCH(r700->VGT_VTX_CNT_EN.u32All);
+	R600_OUT_BATCHX3(r700->VGT_STRMOUT_EN.u32All,
+	/* R600_OUT_BATCH( */ r700->VGT_REUSE_OFF.u32All,
+	/* R600_OUT_BATCH( */ r700->VGT_VTX_CNT_EN.u32All);
 
 	R600_OUT_BATCH_REGVAL(VGT_STRMOUT_BUFFER_EN, r700->VGT_STRMOUT_BUFFER_EN.u32All);
 
@@ -839,15 +839,15 @@ static void r700SendDBState(GLcontext *ctx, struct radeon_state_atom *atom)
 	BEGIN_BATCH_NO_AUTOSTATE(17);
 
 	R600_OUT_BATCH_REGSEQ(DB_STENCIL_CLEAR, 2);
-	R600_OUT_BATCH(r700->DB_STENCIL_CLEAR.u32All);
-	R600_OUT_BATCH(r700->DB_DEPTH_CLEAR.u32All);
+	R600_OUT_BATCHX2(r700->DB_STENCIL_CLEAR.u32All,
+	/* R600_OUT_BATCH( */ r700->DB_DEPTH_CLEAR.u32All);
 
 	R600_OUT_BATCH_REGVAL(DB_DEPTH_CONTROL, r700->DB_DEPTH_CONTROL.u32All);
 	R600_OUT_BATCH_REGVAL(DB_SHADER_CONTROL, r700->DB_SHADER_CONTROL.u32All);
 
 	R600_OUT_BATCH_REGSEQ(DB_RENDER_CONTROL, 2);
-	R600_OUT_BATCH(r700->DB_RENDER_CONTROL.u32All);
-	R600_OUT_BATCH(r700->DB_RENDER_OVERRIDE.u32All);
+	R600_OUT_BATCHX2(r700->DB_RENDER_CONTROL.u32All,
+	/* R600_OUT_BATCH( */ r700->DB_RENDER_OVERRIDE.u32All);
 
 	R600_OUT_BATCH_REGVAL(DB_ALPHA_TO_MASK, r700->DB_ALPHA_TO_MASK.u32All);
 
@@ -863,8 +863,8 @@ static void r700SendStencilState(GLcontext *ctx, struct radeon_state_atom *atom)
 
         BEGIN_BATCH_NO_AUTOSTATE(4);
 	R600_OUT_BATCH_REGSEQ(DB_STENCILREFMASK, 2);
-	R600_OUT_BATCH(r700->DB_STENCILREFMASK.u32All);
-	R600_OUT_BATCH(r700->DB_STENCILREFMASK_BF.u32All);
+	R600_OUT_BATCHX2(r700->DB_STENCILREFMASK.u32All,
+	/* R600_OUT_BATCH( */ r700->DB_STENCILREFMASK_BF.u32All);
 	END_BATCH();
 	COMMIT_BATCH();
 }
@@ -879,21 +879,21 @@ static void r700SendCBState(GLcontext *ctx, struct radeon_state_atom *atom)
 	if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
 		BEGIN_BATCH_NO_AUTOSTATE(11);
 		R600_OUT_BATCH_REGSEQ(CB_CLEAR_RED, 4);
-		R600_OUT_BATCH(r700->CB_CLEAR_RED_R6XX.u32All);
-		R600_OUT_BATCH(r700->CB_CLEAR_GREEN_R6XX.u32All);
-		R600_OUT_BATCH(r700->CB_CLEAR_BLUE_R6XX.u32All);
-		R600_OUT_BATCH(r700->CB_CLEAR_ALPHA_R6XX.u32All);
+		R600_OUT_BATCHX4(r700->CB_CLEAR_RED_R6XX.u32All,
+		/* R600_OUT_BATCH( */ r700->CB_CLEAR_GREEN_R6XX.u32All,
+		/* R600_OUT_BATCH( */ r700->CB_CLEAR_BLUE_R6XX.u32All,
+		/* R600_OUT_BATCH( */ r700->CB_CLEAR_ALPHA_R6XX.u32All);
 		R600_OUT_BATCH_REGSEQ(CB_FOG_RED, 3);
-		R600_OUT_BATCH(r700->CB_FOG_RED_R6XX.u32All);
-		R600_OUT_BATCH(r700->CB_FOG_GREEN_R6XX.u32All);
-		R600_OUT_BATCH(r700->CB_FOG_BLUE_R6XX.u32All);
+		R600_OUT_BATCHX3(r700->CB_FOG_RED_R6XX.u32All,
+		/* R600_OUT_BATCH( */ r700->CB_FOG_GREEN_R6XX.u32All,
+		/* R600_OUT_BATCH( */ r700->CB_FOG_BLUE_R6XX.u32All);
 		END_BATCH();
 	}
 
 	BEGIN_BATCH_NO_AUTOSTATE(7);
 	R600_OUT_BATCH_REGSEQ(CB_TARGET_MASK, 2);
-	R600_OUT_BATCH(r700->CB_TARGET_MASK.u32All);
-	R600_OUT_BATCH(r700->CB_SHADER_MASK.u32All);
+	R600_OUT_BATCHX2(r700->CB_TARGET_MASK.u32All,
+	/* R600_OUT_BATCH( */ r700->CB_SHADER_MASK.u32All);
 	R600_OUT_BATCH_REGVAL(R7xx_CB_SHADER_CONTROL, r700->CB_SHADER_CONTROL.u32All);
 	END_BATCH();
 	COMMIT_BATCH();
@@ -907,10 +907,10 @@ static void r700SendCBCLRCMPState(GLcontext *ctx, struct radeon_state_atom *atom
 
 	BEGIN_BATCH_NO_AUTOSTATE(6);
 	R600_OUT_BATCH_REGSEQ(CB_CLRCMP_CONTROL, 4);
-	R600_OUT_BATCH(r700->CB_CLRCMP_CONTROL.u32All);
-	R600_OUT_BATCH(r700->CB_CLRCMP_SRC.u32All);
-	R600_OUT_BATCH(r700->CB_CLRCMP_DST.u32All);
-	R600_OUT_BATCH(r700->CB_CLRCMP_MSK.u32All);
+	R600_OUT_BATCHX4(r700->CB_CLRCMP_CONTROL.u32All,
+	/* R600_OUT_BATCH( */ r700->CB_CLRCMP_SRC.u32All,
+	/* R600_OUT_BATCH( */ r700->CB_CLRCMP_DST.u32All,
+	/* R600_OUT_BATCH( */ r700->CB_CLRCMP_MSK.u32All);
 	END_BATCH();
 	COMMIT_BATCH();
 }
@@ -956,10 +956,10 @@ static void r700SendCBBlendColorState(GLcontext *ctx, struct radeon_state_atom *
 
 	BEGIN_BATCH_NO_AUTOSTATE(6);
 	R600_OUT_BATCH_REGSEQ(CB_BLEND_RED, 4);
-	R600_OUT_BATCH(r700->CB_BLEND_RED.u32All);
-	R600_OUT_BATCH(r700->CB_BLEND_GREEN.u32All);
-	R600_OUT_BATCH(r700->CB_BLEND_BLUE.u32All);
-	R600_OUT_BATCH(r700->CB_BLEND_ALPHA.u32All);
+	R600_OUT_BATCHX4(r700->CB_BLEND_RED.u32All,
+	/* R600_OUT_BATCH( */ r700->CB_BLEND_GREEN.u32All,
+	/* R600_OUT_BATCH( */ r700->CB_BLEND_BLUE.u32All,
+	/* R600_OUT_BATCH( */ r700->CB_BLEND_ALPHA.u32All);
 	END_BATCH();
 	COMMIT_BATCH();
 }
@@ -973,10 +973,10 @@ static void r700SendSUState(GLcontext *ctx, struct radeon_state_atom *atom)
 	BEGIN_BATCH_NO_AUTOSTATE(9);
 	R600_OUT_BATCH_REGVAL(PA_SU_SC_MODE_CNTL, r700->PA_SU_SC_MODE_CNTL.u32All);
 	R600_OUT_BATCH_REGSEQ(PA_SU_POINT_SIZE, 4);
-	R600_OUT_BATCH(r700->PA_SU_POINT_SIZE.u32All);
-	R600_OUT_BATCH(r700->PA_SU_POINT_MINMAX.u32All);
-	R600_OUT_BATCH(r700->PA_SU_LINE_CNTL.u32All);
-	R600_OUT_BATCH(r700->PA_SU_VTX_CNTL.u32All);
+	R600_OUT_BATCHX4(r700->PA_SU_POINT_SIZE.u32All,
+	/* R600_OUT_BATCH( */ r700->PA_SU_POINT_MINMAX.u32All,
+	/* R600_OUT_BATCH( */ r700->PA_SU_LINE_CNTL.u32All,
+	/* R600_OUT_BATCH( */ r700->PA_SU_VTX_CNTL.u32All);
 	END_BATCH();
 	COMMIT_BATCH();
 
@@ -990,13 +990,13 @@ static void r700SendPolyState(GLcontext *ctx, struct radeon_state_atom *atom)
 
 	BEGIN_BATCH_NO_AUTOSTATE(10);
 	R600_OUT_BATCH_REGSEQ(PA_SU_POLY_OFFSET_DB_FMT_CNTL, 2);
-	R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All);
-	R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_CLAMP.u32All);
+	R600_OUT_BATCHX2(r700->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All,
+	/* R600_OUT_BATCH( */ r700->PA_SU_POLY_OFFSET_CLAMP.u32All);
 	R600_OUT_BATCH_REGSEQ(PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
-	R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_FRONT_SCALE.u32All);
-	R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.u32All);
-	R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_BACK_SCALE.u32All);
-	R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_BACK_OFFSET.u32All);
+	R600_OUT_BATCHX4(r700->PA_SU_POLY_OFFSET_FRONT_SCALE.u32All,
+	/* R600_OUT_BATCH( */ r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.u32All,
+	/* R600_OUT_BATCH( */ r700->PA_SU_POLY_OFFSET_BACK_SCALE.u32All,
+	/* R600_OUT_BATCH( */ r700->PA_SU_POLY_OFFSET_BACK_OFFSET.u32All);
 	END_BATCH();
 	COMMIT_BATCH();
 
@@ -1026,10 +1026,10 @@ static void r700SendGBState(GLcontext *ctx, struct radeon_state_atom *atom)
 
 	BEGIN_BATCH_NO_AUTOSTATE(6);
 	R600_OUT_BATCH_REGSEQ(PA_CL_GB_VERT_CLIP_ADJ, 4);
-	R600_OUT_BATCH(r700->PA_CL_GB_VERT_CLIP_ADJ.u32All);
-	R600_OUT_BATCH(r700->PA_CL_GB_VERT_DISC_ADJ.u32All);
-	R600_OUT_BATCH(r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All);
-	R600_OUT_BATCH(r700->PA_CL_GB_HORZ_DISC_ADJ.u32All);
+	R600_OUT_BATCHX4(r700->PA_CL_GB_VERT_CLIP_ADJ.u32All,
+	/* R600_OUT_BATCH( */ r700->PA_CL_GB_VERT_DISC_ADJ.u32All,
+	/* R600_OUT_BATCH( */ r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All,
+	/* R600_OUT_BATCH( */ r700->PA_CL_GB_HORZ_DISC_ADJ.u32All);
 	END_BATCH();
 	COMMIT_BATCH();
 }
@@ -1043,26 +1043,26 @@ static void r700SendScissorState(GLcontext *ctx, struct radeon_state_atom *atom)
 
 	BEGIN_BATCH_NO_AUTOSTATE(22);
 	R600_OUT_BATCH_REGSEQ(PA_SC_SCREEN_SCISSOR_TL, 2);
-	R600_OUT_BATCH(r700->PA_SC_SCREEN_SCISSOR_TL.u32All);
-	R600_OUT_BATCH(r700->PA_SC_SCREEN_SCISSOR_BR.u32All);
+	R600_OUT_BATCHX2(r700->PA_SC_SCREEN_SCISSOR_TL.u32All,
+	/* R600_OUT_BATCH( */ r700->PA_SC_SCREEN_SCISSOR_BR.u32All);
 
 	R600_OUT_BATCH_REGSEQ(PA_SC_WINDOW_OFFSET, 12);
-	R600_OUT_BATCH(r700->PA_SC_WINDOW_OFFSET.u32All);
-	R600_OUT_BATCH(r700->PA_SC_WINDOW_SCISSOR_TL.u32All);
-	R600_OUT_BATCH(r700->PA_SC_WINDOW_SCISSOR_BR.u32All);
-	R600_OUT_BATCH(r700->PA_SC_CLIPRECT_RULE.u32All);
-	R600_OUT_BATCH(r700->PA_SC_CLIPRECT_0_TL.u32All);
-	R600_OUT_BATCH(r700->PA_SC_CLIPRECT_0_BR.u32All);
-	R600_OUT_BATCH(r700->PA_SC_CLIPRECT_1_TL.u32All);
-	R600_OUT_BATCH(r700->PA_SC_CLIPRECT_1_BR.u32All);
-	R600_OUT_BATCH(r700->PA_SC_CLIPRECT_2_TL.u32All);
-	R600_OUT_BATCH(r700->PA_SC_CLIPRECT_2_BR.u32All);
-	R600_OUT_BATCH(r700->PA_SC_CLIPRECT_3_TL.u32All);
-	R600_OUT_BATCH(r700->PA_SC_CLIPRECT_3_BR.u32All);
+	R600_OUT_BATCHX12(r700->PA_SC_WINDOW_OFFSET.u32All,
+	/* R600_OUT_BATCH( */ r700->PA_SC_WINDOW_SCISSOR_TL.u32All,
+	/* R600_OUT_BATCH( */ r700->PA_SC_WINDOW_SCISSOR_BR.u32All,
+	/* R600_OUT_BATCH( */ r700->PA_SC_CLIPRECT_RULE.u32All,
+	/* R600_OUT_BATCH( */ r700->PA_SC_CLIPRECT_0_TL.u32All,
+	/* R600_OUT_BATCH( */ r700->PA_SC_CLIPRECT_0_BR.u32All,
+	/* R600_OUT_BATCH( */ r700->PA_SC_CLIPRECT_1_TL.u32All,
+	/* R600_OUT_BATCH( */ r700->PA_SC_CLIPRECT_1_BR.u32All,
+	/* R600_OUT_BATCH( */ r700->PA_SC_CLIPRECT_2_TL.u32All,
+	/* R600_OUT_BATCH( */ r700->PA_SC_CLIPRECT_2_BR.u32All,
+	/* R600_OUT_BATCH( */ r700->PA_SC_CLIPRECT_3_TL.u32All,
+	/* R600_OUT_BATCH( */ r700->PA_SC_CLIPRECT_3_BR.u32All);
 
 	R600_OUT_BATCH_REGSEQ(PA_SC_GENERIC_SCISSOR_TL, 2);
-	R600_OUT_BATCH(r700->PA_SC_GENERIC_SCISSOR_TL.u32All);
-	R600_OUT_BATCH(r700->PA_SC_GENERIC_SCISSOR_BR.u32All);
+	R600_OUT_BATCHX2(r700->PA_SC_GENERIC_SCISSOR_TL.u32All,
+	/* R600_OUT_BATCH( */ r700->PA_SC_GENERIC_SCISSOR_BR.u32All);
 	END_BATCH();
 	COMMIT_BATCH();
 }
@@ -1110,14 +1110,14 @@ static void r700SendPSConsts(GLcontext *ctx, struct radeon_state_atom *atom)
 		return;
 
 	BEGIN_BATCH_NO_AUTOSTATE(2 + (r700->ps.num_consts * 4));
-	R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (r700->ps.num_consts * 4)));
+	R600_OUT_BATCHX2(CP_PACKET3(R600_IT_SET_ALU_CONST, (r700->ps.num_consts * 4)),
 	/* assembler map const from very beginning. */
-	R600_OUT_BATCH(SQ_ALU_CONSTANT_PS_OFFSET * 4);
+	/* R600_OUT_BATCH( */ SQ_ALU_CONSTANT_PS_OFFSET * 4);
 	for (i = 0; i < r700->ps.num_consts; i++) {
-		R600_OUT_BATCH(r700->ps.consts[i][0].u32All);
-		R600_OUT_BATCH(r700->ps.consts[i][1].u32All);
-		R600_OUT_BATCH(r700->ps.consts[i][2].u32All);
-		R600_OUT_BATCH(r700->ps.consts[i][3].u32All);
+		R600_OUT_BATCHX4(r700->ps.consts[i][0].u32All,
+		/* R600_OUT_BATCH( */ r700->ps.consts[i][1].u32All,
+		/* R600_OUT_BATCH( */ r700->ps.consts[i][2].u32All,
+		/* R600_OUT_BATCH( */ r700->ps.consts[i][3].u32All);
 	}
 	END_BATCH();
 	COMMIT_BATCH();
@@ -1135,14 +1135,14 @@ static void r700SendVSConsts(GLcontext *ctx, struct radeon_state_atom *atom)
 		return;
 
 	BEGIN_BATCH_NO_AUTOSTATE(2 + (r700->vs.num_consts * 4));
-	R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (r700->vs.num_consts * 4)));
+	R600_OUT_BATCHX2(CP_PACKET3(R600_IT_SET_ALU_CONST, (r700->vs.num_consts * 4)),
 	/* assembler map const from very beginning. */
-	R600_OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4);
+	/* R600_OUT_BATCH( */ SQ_ALU_CONSTANT_VS_OFFSET * 4);
 	for (i = 0; i < r700->vs.num_consts; i++) {
-		R600_OUT_BATCH(r700->vs.consts[i][0].u32All);
-		R600_OUT_BATCH(r700->vs.consts[i][1].u32All);
-		R600_OUT_BATCH(r700->vs.consts[i][2].u32All);
-		R600_OUT_BATCH(r700->vs.consts[i][3].u32All);
+		R600_OUT_BATCHX4(r700->vs.consts[i][0].u32All,
+		/* R600_OUT_BATCH( */ r700->vs.consts[i][1].u32All,
+		/* R600_OUT_BATCH( */ r700->vs.consts[i][2].u32All,
+		/* R600_OUT_BATCH( */ r700->vs.consts[i][3].u32All);
 	}
 	END_BATCH();
 	COMMIT_BATCH();
@@ -1165,10 +1165,10 @@ static void r700SendQueryBegin(GLcontext *ctx, struct radeon_state_atom *atom)
 				      0, RADEON_GEM_DOMAIN_GTT);
 
 	BEGIN_BATCH_NO_AUTOSTATE(4 + 2);
-	R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2));
-	R600_OUT_BATCH(ZPASS_DONE);
-	R600_OUT_BATCH(query->curr_offset); /* hw writes qwords */
-	R600_OUT_BATCH(0x00000000);
+	R600_OUT_BATCHX4(CP_PACKET3(R600_IT_EVENT_WRITE, 2),
+	/* R600_OUT_BATCH( */ ZPASS_DONE,
+	/* R600_OUT_BATCH( */ query->curr_offset, /* hw writes qwords */
+	/* R600_OUT_BATCH( */ 0x00000000);
 	R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0);
 	END_BATCH();
 	query->emitted_begin = GL_TRUE;
diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c
index 1929b7c..ba889b7 100644
--- a/src/mesa/drivers/dri/r600/r700_render.c
+++ b/src/mesa/drivers/dri/r600/r700_render.c
@@ -71,9 +71,9 @@ void r700WaitForIdle(context_t *context)
     radeon_print(RADEON_RENDER | RADEON_STATE, RADEON_TRACE, "%s\n", __func__);
     BEGIN_BATCH_NO_AUTOSTATE(3);
 
-    R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
-    R600_OUT_BATCH(mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX);
-    R600_OUT_BATCH(WAIT_3D_IDLE_bit);
+    R600_OUT_BATCHX3(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1),
+    /* R600_OUT_BATCH( */ mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX,
+    /* R600_OUT_BATCH( */ WAIT_3D_IDLE_bit);
 
     END_BATCH();
     COMMIT_BATCH();
@@ -85,12 +85,12 @@ void r700WaitForIdleClean(context_t *context)
     radeon_print(RADEON_RENDER | RADEON_STATE, RADEON_TRACE, "%s\n", __func__);
     BEGIN_BATCH_NO_AUTOSTATE(5);
 
-    R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
-    R600_OUT_BATCH(CACHE_FLUSH_AND_INV_EVENT);
+    R600_OUT_BATCHX5(CP_PACKET3(R600_IT_EVENT_WRITE, 0),
+    /* R600_OUT_BATCH( */ CACHE_FLUSH_AND_INV_EVENT,
 
-    R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
-    R600_OUT_BATCH(mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX);
-    R600_OUT_BATCH(WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
+    /* R600_OUT_BATCH( */ CP_PACKET3(R600_IT_SET_CONFIG_REG, 1),
+    /* R600_OUT_BATCH( */ mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX,
+    /* R600_OUT_BATCH( */ WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
 
     END_BATCH();
     COMMIT_BATCH();
@@ -103,15 +103,15 @@ void r700Start3D(context_t *context)
     if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
     {
         BEGIN_BATCH_NO_AUTOSTATE(2);
-        R600_OUT_BATCH(CP_PACKET3(R600_IT_START_3D_CMDBUF, 0));
-        R600_OUT_BATCH(0);
+        R600_OUT_BATCHX2(CP_PACKET3(R600_IT_START_3D_CMDBUF, 0),
+        /* R600_OUT_BATCH( */ 0);
         END_BATCH();
     }
 
     BEGIN_BATCH_NO_AUTOSTATE(3);
-    R600_OUT_BATCH(CP_PACKET3(R600_IT_CONTEXT_CONTROL, 1));
-    R600_OUT_BATCH(0x80000000);
-    R600_OUT_BATCH(0x80000000);
+    R600_OUT_BATCHX3(CP_PACKET3(R600_IT_CONTEXT_CONTROL, 1),
+    /* R600_OUT_BATCH( */ 0x80000000,
+    /* R600_OUT_BATCH( */ 0x80000000);
     END_BATCH();
 
     COMMIT_BATCH();
@@ -136,11 +136,11 @@ GLboolean r700SyncSurf(context_t *context,
 	    cp_coher_size = ((pbo->size + 255) >> 8);
 
     BEGIN_BATCH_NO_AUTOSTATE(5 + 2);
-    R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_SYNC, 3));
-    R600_OUT_BATCH(sync_type);
-    R600_OUT_BATCH(cp_coher_size);
-    R600_OUT_BATCH(0);
-    R600_OUT_BATCH(10);
+    R600_OUT_BATCHX5(CP_PACKET3(R600_IT_SURFACE_SYNC, 3),
+    /* R600_OUT_BATCH( */ sync_type,
+    /* R600_OUT_BATCH( */ cp_coher_size,
+    /* R600_OUT_BATCH( */ 0,
+    /* R600_OUT_BATCH( */ 10);
     R600_OUT_BATCH_RELOC(0,
 			 pbo,
 			 0,
@@ -287,19 +287,19 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim
     BEGIN_BATCH_NO_AUTOSTATE(total_emit);
     // prim
     R600_OUT_BATCH_REGSEQ(VGT_PRIMITIVE_TYPE, 1);
-    R600_OUT_BATCH(vgt_primitive_type);
+    R600_OUT_BATCHX10(vgt_primitive_type,
     // index type
-    R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
-    R600_OUT_BATCH(vgt_index_type);
+    /* R600_OUT_BATCH( */ CP_PACKET3(R600_IT_INDEX_TYPE, 0),
+    /* R600_OUT_BATCH( */ vgt_index_type,
     // num instances
-    R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
-    R600_OUT_BATCH(1);
+    /* R600_OUT_BATCH( */ CP_PACKET3(R600_IT_NUM_INSTANCES, 0),
+    /* R600_OUT_BATCH( */ 1,
     // draw packet
-    R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX, 3));
-    R600_OUT_BATCH(context->ind_buf.bo_offset);
-    R600_OUT_BATCH(0);
-    R600_OUT_BATCH(vgt_num_indices);
-    R600_OUT_BATCH(vgt_draw_initiator);
+    /* R600_OUT_BATCH( */ CP_PACKET3(R600_IT_DRAW_INDEX, 3),
+    /* R600_OUT_BATCH( */ context->ind_buf.bo_offset,
+    /* R600_OUT_BATCH( */ 0,
+    /* R600_OUT_BATCH( */ vgt_num_indices,
+    /* R600_OUT_BATCH( */ vgt_draw_initiator);
     R600_OUT_BATCH_RELOC(context->ind_buf.bo_offset,
 			 context->ind_buf.bo,
 			 context->ind_buf.bo_offset,
@@ -369,27 +369,27 @@ static void r700RunRenderPrimitiveImmediate(GLcontext * ctx, int start, int end,
     BEGIN_BATCH_NO_AUTOSTATE(total_emit);
     // prim
     R600_OUT_BATCH_REGSEQ(VGT_PRIMITIVE_TYPE, 1);
-    R600_OUT_BATCH(vgt_primitive_type);
+    R600_OUT_BATCHX5(vgt_primitive_type,
     // index type
-    R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
-    R600_OUT_BATCH(vgt_index_type);
+    /* R600_OUT_BATCH( */ CP_PACKET3(R600_IT_INDEX_TYPE, 0),
+    /* R600_OUT_BATCH( */ vgt_index_type,
     // num instances
-    R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
-    R600_OUT_BATCH(1);
+    /* R600_OUT_BATCH( */ CP_PACKET3(R600_IT_NUM_INSTANCES, 0),
+    /* R600_OUT_BATCH( */ 1);
     // draw packet
     if(start == 0)
     {
-        R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1));
-        R600_OUT_BATCH(vgt_num_indices);
-        R600_OUT_BATCH(vgt_draw_initiator);
+        R600_OUT_BATCHX3(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1),
+        /* R600_OUT_BATCH( */ vgt_num_indices,
+        /* R600_OUT_BATCH( */ vgt_draw_initiator);
     }
     else
     {
 	if (num_indices > 0xffff)
         {
-	    R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (num_indices + 1)));
-	    R600_OUT_BATCH(vgt_num_indices);
-	    R600_OUT_BATCH(vgt_draw_initiator);
+	    R600_OUT_BATCHX3(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (num_indices + 1)),
+	    /* R600_OUT_BATCH( */ vgt_num_indices,
+	    /* R600_OUT_BATCH( */ vgt_draw_initiator);
 	    for (i = start; i < (start + num_indices); i++)
 	    {
 		R600_OUT_BATCH(i);
@@ -397,9 +397,9 @@ static void r700RunRenderPrimitiveImmediate(GLcontext * ctx, int start, int end,
 	}
 	else
         {
-	    R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (((num_indices + 1) / 2) + 1)));
-	    R600_OUT_BATCH(vgt_num_indices);
-	    R600_OUT_BATCH(vgt_draw_initiator);
+	    R600_OUT_BATCHX3(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (((num_indices + 1) / 2) + 1)),
+	    /* R600_OUT_BATCH( */ vgt_num_indices,
+	    /* R600_OUT_BATCH( */ vgt_draw_initiator);
 	    for (i = start; i < (start + num_indices); i += 2)
 	    {
 		if ((i + 1) == (start + num_indices))