`default_nettype none
//
// de1floppy
//
module de1floppy (
	CLOCK_50,
	
	// from floppy drive
	nINDEX,	nCHANGE, nRDY, nRDATA, nTRK0, nWPROT,
	
	// to floppy drive
	nSEL0, nSEL1, nMTRON, DIR, nSTEP, nWDATA, nWGATE, nSIDE,
	
	// indication
	LEDG, LEDR, HEX0, HEX1, HEX2, HEX3,
	
	// controls
	KEY, SW,
	
	// VGA
	VGA_HS, VGA_VS, VGA_R, VGA_G, VGA_B,
	
	// RS-232
	UART_TXD, UART_RXD
	
	);	// 25:10

input CLOCK_50;

input nINDEX, nCHANGE, nRDY, nRDATA, nTRK0, nWPROT;

output nSEL0, nSEL1, nMTRON, DIR, nSTEP, nWDATA, nWGATE, nSIDE;

output [7:0] LEDG;
output [9:0] LEDR;
output [6:0] HEX0;
output [6:0] HEX1; 
output [6:0] HEX2;
output [6:0] HEX3;
input [3:0] KEY;
input [9:0] SW;
output VGA_HS, VGA_VS;
output [3:0] VGA_R;
output [3:0] VGA_G;
output [3:0] VGA_B;
output 	UART_TXD;
inout	UART_RXD;

// ---------------------------------------------------------------------------------
/*
            addr_out :  out std_logic_vector(15 downto 0);
              
            inta :      out std_logic;
            inte :      out std_logic;
            halt :      out std_logic;                
            intr :      in std_logic;
            
            vma :       out std_logic;
            io :        out std_logic;
            rd :        out std_logic;
            wr :        out std_logic;
            fetch :     out std_logic;
            data_in :   in std_logic_vector(7 downto 0);  
            data_out :  out std_logic_vector(7 downto 0);

            clk :       in std_logic;
            reset :     in std_logic );
*/

wire [15:0] addr_out;
wire vma;
wire io;
wire rd;
wire wr;
wire fetch;
wire [7:0] data_in;
wire [7:0] data_out;
wire [7:0] output_port;

wire clk = SW [0] ? counter [23] : clk_25mhz;
wire clk2 = SW [0] ? counter [22] : clk_50mhz;


light8080 light8080_i (
	.addr_out (addr_out [15:0]),
	
	.intr (1'b0),
	.vma (vma),
	.io (io),
	.rd (rd),
	.wr (wr),
	.fetch (fetch),
	
	.data_in (data_in [7:0]),
	.data_out (data_out [7:0]),
	
	.clk (clk),
	.reset (reset)
	
	);

memory memory_i (
	.clk (clk),
	.clk2 (clk2),
	
	.reset (reset),
	
	.addr (addr_out [15:0]),
	.vma (vma),
	.rd (rd),
	.wr (wr),
	.io (io),
	.data_in (data_out [7:0]),
	.data_out (data_in [7:0]),
	
	.output_port (output_port [7:0]),
	.floppy_input_port ({nINDEX, nCHANGE, nRDY, nRDATA, nTRK0, nWPROT, 2'b0}),
	.floppy_output_port ({nSEL0, nSEL1, nMTRON, DIR, nSTEP, nWDATA, nWGATE, nSIDE}),
	
	.uart_txd (UART_TXD)
	
	);



SEG7_LUT_4 hexdisplay (		
	.iDIG ({addr_out [7:0], data_in [7:0]}),
	.oSEG0 (HEX0), .oSEG1 (HEX1), .oSEG2 (HEX2), .oSEG3 (HEX3)
	);


vga mydisplay (.clk (clk_25mhz), .vga_h_sync (VGA_HS), .vga_v_sync (VGA_VS), .R (VGA_R [3:0]), .G (VGA_G [3:0]), .B (VGA_B [3:0]));




// ---------------------------------------------------------------------------------

wire clk_50mhz, clk_25mhz;
wire reset = ~KEY [0];

parameter	FD_IDLE			= 4'b0000,
			FD_SELECT		= 4'b0001,
			FD_MOTOR_ON		= 4'b0010,
			FD_RDY_WAIT		= 4'b0011,
			FD_READ			= 4'b0100;

reg [3:0] fd_state_r;

pll my_pll (.inclk0 (CLOCK_50), .c0 (clk_25mhz), .c1 (clk_50mhz));

reg nINDEX_r, nCHANGE_r, nRDY_r, nRDATA_r, nTRK0_r, nWPROT_r;

reg nSEL0_r;

always @(posedge clk_25mhz) begin
	nINDEX_r <= nINDEX;
	nCHANGE_r <= nCHANGE;
	nRDY_r <= nRDY;
	nRDATA_r <= nRDATA;
	nTRK0_r <= nTRK0;
	nWPROT_r <= nWPROT;
end


parameter ONESEC = 25'd20000000;
parameter HALFSEC = 25'd100000;

reg [24:0] cntr;
/*
//
// fd_state_r
//
always @(posedge clk_25mhz) begin
	if (reset) begin
		fd_state_r <= FD_IDLE;
		cntr <= 0;
		nSEL0_r <= 1'b1;
	end
	else begin
		case (fd_state_r)
			
			FD_IDLE: begin
				if (cntr == HALFSEC) begin
					fd_state_r <= FD_SELECT;
					nSEL0_r <= 1'b0;
					cntr <= 0;
				end
				cntr <= cntr + 1'b1;
			end
			
			FD_SELECT: begin
				if (cntr == HALFSEC) begin
					fd_state_r <= FD_IDLE;
					nSEL0_r <= 1'b1;
					cntr <= 0;
				end
				cntr <= cntr + 1'b1;
			end
			
			FD_MOTOR_ON:	;
			FD_RDY_WAIT:	;
			FD_READ:		;
		endcase
	end
end

*/

reg [25:0] counter;
always @(posedge clk_25mhz) begin
	counter <= counter + 1'b1;
end


reg [15:0] cntr_1khz;
wire bingo = cntr_1khz == 16'd20000;
always @(posedge clk) begin
	if (reset)
		cntr_1khz <= 0;
	else begin
		if (bingo)
			cntr_1khz <= 0;
		else
			cntr_1khz <= cntr_1khz + 1'b1;
	end
end

//assign {nSEL0, nSEL1, nMTRON, DIR, nSTEP, nWDATA, nWGATE, nSIDE} = {counter [20:14], bingo};
//assign nSEL0 = nSEL0_r;

assign LEDG [0] = counter [24];

assign LEDG [5] = nTRK0;
assign LEDG [6] = nCHANGE;
assign LEDG [7] = nRDY;


//assign LEDR [5:0] = {nINDEX, nCHANGE, nRDY, nRDATA, nTRK0, nWPROT};
//assign LEDR [5:0] = {nINDEX_r, nCHANGE_r, nRDY_r, nRDATA_r, nTRK0_r, nWPROT_r};
assign LEDR [7:0] = output_port [7:0];

assign LEDR [8] = rd;
assign LEDR [9] = wr;

endmodule