module memory (clk, clk2, reset, addr, rd, wr, io, vma, data_in, data_out, output_port, floppy_input_port, floppy_output_port,
	uart_txd);

input clk, clk2;
input reset;
input [15:0] addr;
input rd, wr, io, vma;
input [7:0] data_in;
output reg [7:0] data_out;
output reg [7:0] output_port;
output reg [7:0] floppy_output_port;
input [7:0] floppy_input_port;

output	uart_txd;

/*
	.floppy_input_port ({nINDEX, nCHANGE, nRDY, nRDATA, nTRK0, nWPROT, 2'b0}),
	.floppy_output_port ({nSEL0, nSEL1, nMTRON, DIR, nSTEP, nWDATA, nWGATE, nSIDE})

*/

parameter	LED_PORT		= 8'hF0;
parameter	FLOPPY_PORT_OUT	= 8'hF1;
parameter	FLOPPY_PORT_IN	= 8'hF1;
parameter	UART_DATA		= 8'hF2;

//
//		bit 7	bit 6	bit 5	bit 4	bit 3	bit 2	bit 1	bit 0
//		-------	-------	-------	-------	-------	-------	-------	-------
//		BUSY
//
parameter	UART_CTRL		= 8'hF3;



reg [7:0] txdata;
reg txstart;
wire uart_txd_busy;

async_transmitter uart (.clk (clk), .TxD_start (txstart), .TxD_data (txdata [7:0]), .TxD (uart_txd), .TxD_busy (uart_txd_busy));




always @(posedge clk or posedge reset) begin		
	if (reset) begin
		data_out [7:0] <= 8'h00;
		output_port [7:0] <= 8'h00;
		floppy_output_port [7:0] <= 8'hff;
				
		txstart <= 1'b0;
	end
	else begin
		if (io) begin
		// ---------------------------- I/O ---------------------------------
			if (wr) begin
			// ------------------------ write -------------------------------
				case (addr [7:0])
					LED_PORT:			output_port [7:0] <= data_in [7:0];
					FLOPPY_PORT_OUT:	floppy_output_port [7:0] <= data_in [7:0];
					UART_DATA:	begin
										txdata [7:0] <= data_in [7:0];
										txstart <= 1'b1;
					end
				endcase
			end
			else begin
			// ------------------------ read --------------------------------							
			
				case (addr [7:0])
					LED_PORT:			data_out [7:0] <= output_port [7:0];
					FLOPPY_PORT_OUT:	data_out [7:0] <= floppy_output_port [7:0];
					FLOPPY_PORT_IN:		data_out [7:0] <= floppy_input_port [7:0];
					UART_CTRL:			data_out [7:0] <= {uart_txd_busy, 7'b0};
				endcase
			end
		end
		else begin
		// ----------------------------- memory -----------------------------
		
			txstart <= 1'b0;
			
			if (rd) begin
				data_out [7:0] <= mem_q [7:0];

			end
		end
	end
end





wire [7:0] mem_q;

mem mem_i (
	.address (addr [15:0]),
	
//	.clock (clk2),
	.clock (~clk),
	.data (data_in [7:0]),
	.wren (wr),
	.q (mem_q [7:0])
);


endmodule