From 1748509e44fe279d2d5ed18ff0b9fa5a0cffb040 Mon Sep 17 00:00:00 2001 From: bzo Date: Tue, 21 Dec 2010 10:41:48 -0800 Subject: [PATCH] fix for sleep mode of 1 when overclocking PLL2 --- arch/arm/mach-msm/acpuclock.c | 14 ++++++++++++-- 1 files changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-msm/acpuclock.c b/arch/arm/mach-msm/acpuclock.c index ab41d06..d367b0f 100644 --- a/arch/arm/mach-msm/acpuclock.c +++ b/arch/arm/mach-msm/acpuclock.c @@ -356,7 +356,7 @@ writel((1 << 7) | (vdd << 3), A11S_VDD_SVS_PLEVEL_ADDR); /* Set proper dividers for the given clock speed. */ static void acpuclk_set_div(const struct clkctl_acpu_speed *hunt_s) { - uint32_t reg_clkctl, reg_clksel, clk_div, src_sel; + uint32_t reg_clkctl, reg_clksel, clk_div, src_sel, reg_clk_mult; reg_clksel = readl(A11S_CLK_SEL_ADDR); @@ -374,7 +374,17 @@ static void acpuclk_set_div(const struct clkctl_acpu_speed *hunt_s) { reg_clksel |= (hunt_s->ahbclk_div << 1); writel(reg_clksel, A11S_CLK_SEL_ADDR); } - + + /* check PLL2 for overclocking. A9 can reset it 1056mhz/2 operation + for normal 528mhz operation */ + if (oc_freq_khz && hunt_s->pll == ACPU_PLL_2) { + reg_clk_mult = readl(MSM_CLK_CTL_BASE+0x33c); + if (reg_clk_mult != oc_freq_khz / 19200) { + writel(oc_freq_khz / 19200, MSM_CLK_CTL_BASE+0x33c); + mdelay(50); + } + } + /* Program clock source and divider */ reg_clkctl = readl(A11S_CLK_CNTL_ADDR); reg_clkctl &= ~(0xFF << (8 * src_sel)); -- 1.6.3.3