Initializing cgroup subsys cpu Linux version 2.6.39-rc7+ (root@multivac) (gcc version 4.5.2 (Gentoo 4.5.2 p1.1, pie-0.4.5) ) #58 SMP PREEMPT Fri May 13 18:46:51 CEST 2011 Command line: root=/dev/sdg6 BIOS-provided physical RAM map: BIOS-e820: 0000000000000000 - 000000000009a800 (usable) BIOS-e820: 000000000009a800 - 00000000000a0000 (reserved) BIOS-e820: 00000000000e0000 - 0000000000100000 (reserved) BIOS-e820: 0000000000100000 - 00000000cefcf000 (usable) BIOS-e820: 00000000cefcf000 - 00000000cf026000 (ACPI NVS) BIOS-e820: 00000000cf026000 - 00000000cf5a2000 (reserved) BIOS-e820: 00000000cf5a2000 - 00000000cf5b3000 (ACPI NVS) BIOS-e820: 00000000cf5b3000 - 00000000cf5ca000 (reserved) BIOS-e820: 00000000cf5ca000 - 00000000cf5cc000 (usable) BIOS-e820: 00000000cf5cc000 - 00000000cf5d4000 (reserved) BIOS-e820: 00000000cf5d4000 - 00000000cf5de000 (ACPI NVS) BIOS-e820: 00000000cf5de000 - 00000000cf63a000 (reserved) BIOS-e820: 00000000cf63a000 - 00000000cf67d000 (ACPI NVS) BIOS-e820: 00000000cf67d000 - 00000000cf800000 (usable) BIOS-e820: 00000000fed1c000 - 00000000fed20000 (reserved) BIOS-e820: 00000000ff000000 - 0000000100000000 (reserved) BIOS-e820: 0000000100000000 - 000000022f800000 (usable) NX (Execute Disable) protection: active DMI 2.6 present. DMI: System manufacturer System Product Name/P8P67 PRO, BIOS 1502 03/02/2011 e820 update range: 0000000000000000 - 0000000000010000 (usable) ==> (reserved) e820 remove range: 00000000000a0000 - 0000000000100000 (usable) No AGP bridge found last_pfn = 0x22f800 max_arch_pfn = 0x400000000 MTRR default type: uncachable MTRR fixed ranges enabled: 00000-9FFFF write-back A0000-BFFFF uncachable C0000-D3FFF write-protect D4000-E7FFF uncachable E8000-FFFFF write-protect MTRR variable ranges enabled: 0 base 000000000 mask E00000000 write-back 1 base 200000000 mask FC0000000 write-back 2 base 0D0000000 mask FF0000000 uncachable 3 base 0E0000000 mask FE0000000 uncachable 4 base 22F800000 mask FFF800000 uncachable 5 base 230000000 mask FF0000000 uncachable 6 disabled 7 disabled 8 disabled 9 disabled x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106 original variable MTRRs reg 0, base: 0GB, range: 8GB, type WB reg 1, base: 8GB, range: 1GB, type WB reg 2, base: 3328MB, range: 256MB, type UC reg 3, base: 3584MB, range: 512MB, type UC reg 4, base: 8952MB, range: 8MB, type UC reg 5, base: 8960MB, range: 256MB, type UC total RAM covered: 8184M Found optimal setting for mtrr clean up gran_size: 64K chunk_size: 16M num_reg: 7 lose cover RAM: 0G New variable MTRRs reg 0, base: 0GB, range: 2GB, type WB reg 1, base: 2GB, range: 1GB, type WB reg 2, base: 3GB, range: 256MB, type WB reg 3, base: 4GB, range: 4GB, type WB reg 4, base: 8GB, range: 512MB, type WB reg 5, base: 8704MB, range: 256MB, type WB reg 6, base: 8952MB, range: 8MB, type UC e820 update range: 00000000d0000000 - 0000000100000000 (usable) ==> (reserved) last_pfn = 0xcf800 max_arch_pfn = 0x400000000 initial memory mapped : 0 - 20000000 Base memory trampoline at [ffff880000098000] 98000 size 8192 init_memory_mapping: 0000000000000000-00000000cf800000 0000000000 - 00cf800000 page 2M kernel direct mapping tables up to cf800000 @ cf7fb000-cf800000 init_memory_mapping: 0000000100000000-000000022f800000 0100000000 - 022f800000 page 2M kernel direct mapping tables up to 22f800000 @ 22f7f6000-22f800000 ACPI: RSDP 00000000000f0420 00024 (v02 ALASKA) ACPI: XSDT 00000000cf01d068 0004C (v01 ALASKA A M I 01072009 AMI 00010013) ACPI: FACP 00000000cf0259d8 000F4 (v04 ALASKA A M I 01072009 AMI 00010013) ACPI: DSDT 00000000cf01d140 08891 (v02 ALASKA A M I 00000000 INTL 20051117) ACPI: FACS 00000000cf5d5f80 00040 ACPI: APIC 00000000cf025ad0 00092 (v03 ALASKA A M I 01072009 AMI 00010013) ACPI: SSDT 00000000cf025b68 001D6 (v01 AMICPU PROC 00000001 MSFT 03000001) ACPI: MCFG 00000000cf025d40 0003C (v01 ALASKA A M I 01072009 MSFT 00000097) ACPI: HPET 00000000cf025d80 00038 (v01 ALASKA A M I 01072009 AMI. 00000004) ACPI: Local APIC address 0xfee00000 [ffffea0000000000-ffffea0007bfffff] PMD -> [ffff88021c000000-ffff8802231fffff] on node 0 Zone PFN ranges: DMA 0x00000010 -> 0x00001000 DMA32 0x00001000 -> 0x00100000 Normal 0x00100000 -> 0x0022f800 Movable zone start PFN for each node early_node_map[5] active PFN ranges 0: 0x00000010 -> 0x0000009a 0: 0x00000100 -> 0x000cefcf 0: 0x000cf5ca -> 0x000cf5cc 0: 0x000cf67d -> 0x000cf800 0: 0x00100000 -> 0x0022f800 On node 0 totalpages: 2091230 DMA zone: 56 pages used for memmap DMA zone: 2 pages reserved DMA zone: 3920 pages, LIFO batch:0 DMA32 zone: 14280 pages used for memmap DMA32 zone: 829836 pages, LIFO batch:31 Normal zone: 16996 pages used for memmap Normal zone: 1226140 pages, LIFO batch:31 ACPI: PM-Timer IO Port: 0x408 ACPI: Local APIC address 0xfee00000 ACPI: LAPIC (acpi_id[0x01] lapic_id[0x00] enabled) ACPI: LAPIC (acpi_id[0x02] lapic_id[0x02] enabled) ACPI: LAPIC (acpi_id[0x03] lapic_id[0x04] enabled) ACPI: LAPIC (acpi_id[0x04] lapic_id[0x06] enabled) ACPI: LAPIC (acpi_id[0x05] lapic_id[0x01] enabled) ACPI: LAPIC (acpi_id[0x06] lapic_id[0x03] enabled) ACPI: LAPIC (acpi_id[0x07] lapic_id[0x05] enabled) ACPI: LAPIC (acpi_id[0x08] lapic_id[0x07] enabled) ACPI: LAPIC_NMI (acpi_id[0xff] high edge lint[0x1]) ACPI: IOAPIC (id[0x00] address[0xfec00000] gsi_base[0]) IOAPIC[0]: apic_id 0, version 32, address 0xfec00000, GSI 0-23 ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level) ACPI: IRQ0 used by override. ACPI: IRQ2 used by override. ACPI: IRQ9 used by override. Using ACPI (MADT) for SMP configuration information ACPI: HPET id: 0x8086a701 base: 0xfed00000 SMP: Allowing 8 CPUs, 0 hotplug CPUs nr_irqs_gsi: 40 Allocating PCI resources starting at cf800000 (gap: cf800000:2f51c000) setup_percpu: NR_CPUS:8 nr_cpumask_bits:8 nr_cpu_ids:8 nr_node_ids:1 PERCPU: Embedded 26 pages/cpu @ffff88022f400000 s75328 r8192 d22976 u262144 pcpu-alloc: s75328 r8192 d22976 u262144 alloc=1*2097152 pcpu-alloc: [0] 0 1 2 3 4 5 6 7 Built 1 zonelists in Zone order, mobility grouping on. Total pages: 2059896 Kernel command line: root=/dev/sdg6 PID hash table entries: 4096 (order: 3, 32768 bytes) Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes) Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes) xsave/xrstor: enabled xstate_bv 0x7, cntxt size 0x340 Checking aperture... No AGP bridge found Memory: 8158364k/9166848k available (4878k kernel code, 801928k absent, 206556k reserved, 4085k data, 484k init) SLUB: Genslabs=15, HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1 Preemptable hierarchical RCU implementation. RCU-based detection of stalled CPUs is disabled. Verbose stalled-CPUs detection is disabled. NR_IRQS:512 Extended CMOS year: 2000 Console: colour VGA+ 80x25 console [tty0] enabled hpet clockevent registered Fast TSC calibration failed TSC: Unable to calibrate against PIT TSC: using HPET reference calibration Detected 3400.017 MHz processor. Calibrating delay loop (skipped), value calculated using timer frequency.. 6800.03 BogoMIPS (lpj=3400017) pid_max: default: 32768 minimum: 301 Mount-cache hash table entries: 256 Initializing cgroup subsys cpuacct Initializing cgroup subsys blkio CPU: Physical Processor ID: 0 CPU: Processor Core ID: 0 mce: CPU supports 9 MCE banks CPU0: Thermal monitoring enabled (TM1) using mwait in idle threads. Freeing SMP alternatives: 16k freed ACPI: Core revision 20110316 Setting APIC routing to flat ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1 CPU0: Intel(R) Core(TM) i7-2600K CPU @ 3.40GHz stepping 07 Performance Events: PEBS fmt1+, SandyBridge events, Intel PMU driver. ... version: 3 ... bit width: 48 ... generic registers: 4 ... value mask: 0000ffffffffffff ... max period: 000000007fffffff ... fixed-purpose events: 3 ... event mask: 000000070000000f Booting Node 0, Processors #1 smpboot cpu 1: start_ip = 98000 #2 smpboot cpu 2: start_ip = 98000 #3 smpboot cpu 3: start_ip = 98000 #4 smpboot cpu 4: start_ip = 98000 #5 smpboot cpu 5: start_ip = 98000 #6 smpboot cpu 6: start_ip = 98000 #7 Ok. smpboot cpu 7: start_ip = 98000 Brought up 8 CPUs Total of 8 processors activated (54392.65 BogoMIPS). NET: Registered protocol family 16 ACPI: bus type pci registered PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000) PCI: not using MMCONFIG PCI: Using configuration type 1 for base access bio: create slab at 0 ACPI: EC: Look up EC in DSDT ACPI: Executed 1 blocks of module-level executable AML code ACPI Error: [RAMB] Namespace lookup failure, AE_NOT_FOUND (20110316/psargs-359) ACPI Exception: AE_NOT_FOUND, Could not execute arguments for [RAMW] (Region) (20110316/nsinit-349) ACPI: SSDT 00000000cf5dd898 006F4 (v01 AMI IST 00000001 MSFT 03000001) ACPI: Dynamic OEM Table Load: ACPI: SSDT (null) 006F4 (v01 AMI IST 00000001 MSFT 03000001) ACPI: SSDT 00000000cf5d4d98 000E4 (v01 AMI CST 00000001 MSFT 03000001) ACPI: Dynamic OEM Table Load: ACPI: SSDT (null) 000E4 (v01 AMI CST 00000001 MSFT 03000001) ACPI: Interpreter enabled ACPI: (supports S0 S5) ACPI: Using IOAPIC for interrupt routing PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000) PCI: MMCONFIG at [mem 0xe0000000-0xe3ffffff] reserved in ACPI motherboard resources [Firmware Bug]: ACPI: BIOS _OSI(Linux) query ignored ACPI: EC: GPE = 0x18, I/O: command/status = 0x66, data = 0x62 PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff]) pci_root PNP0A08:00: host bridge window [io 0x0000-0x0cf7] pci_root PNP0A08:00: host bridge window [io 0x0d00-0xffff] pci_root PNP0A08:00: host bridge window [mem 0x000a0000-0x000bffff] pci_root PNP0A08:00: host bridge window [mem 0x000c8000-0x000dffff] pci_root PNP0A08:00: host bridge window [mem 0xd0000000-0xffffffff] pci 0000:00:00.0: [8086:0100] type 0 class 0x000600 pci 0000:00:01.0: [8086:0101] type 1 class 0x000604 pci 0000:00:01.0: PME# supported from D0 D3hot D3cold pci 0000:00:01.0: PME# disabled pci 0000:00:16.0: [8086:1c3a] type 0 class 0x000780 pci 0000:00:16.0: reg 10: [mem 0xf9625000-0xf962500f 64bit] pci 0000:00:16.0: PME# supported from D0 D3hot D3cold pci 0000:00:16.0: PME# disabled pci 0000:00:19.0: [8086:1503] type 0 class 0x000200 pci 0000:00:19.0: reg 10: [mem 0xf9600000-0xf961ffff] pci 0000:00:19.0: reg 14: [mem 0xf9624000-0xf9624fff] pci 0000:00:19.0: reg 18: [io 0xf040-0xf05f] pci 0000:00:19.0: PME# supported from D0 D3hot D3cold pci 0000:00:19.0: PME# disabled pci 0000:00:1a.0: [8086:1c2d] type 0 class 0x000c03 pci 0000:00:1a.0: reg 10: [mem 0xf9623000-0xf96233ff] pci 0000:00:1a.0: PME# supported from D0 D3hot D3cold pci 0000:00:1a.0: PME# disabled pci 0000:00:1c.0: [8086:1c10] type 1 class 0x000604 pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold pci 0000:00:1c.0: PME# disabled pci 0000:00:1c.1: [8086:1c12] type 1 class 0x000604 pci 0000:00:1c.1: PME# supported from D0 D3hot D3cold pci 0000:00:1c.1: PME# disabled pci 0000:00:1c.2: [8086:1c14] type 1 class 0x000604 pci 0000:00:1c.2: PME# supported from D0 D3hot D3cold pci 0000:00:1c.2: PME# disabled pci 0000:00:1c.3: [8086:1c16] type 1 class 0x000604 pci 0000:00:1c.3: PME# supported from D0 D3hot D3cold pci 0000:00:1c.3: PME# disabled pci 0000:00:1c.4: [8086:1c18] type 1 class 0x000604 pci 0000:00:1c.4: PME# supported from D0 D3hot D3cold pci 0000:00:1c.4: PME# disabled pci 0000:00:1c.6: [8086:244e] type 1 class 0x000604 pci 0000:00:1c.6: PME# supported from D0 D3hot D3cold pci 0000:00:1c.6: PME# disabled pci 0000:00:1c.7: [8086:1c1e] type 1 class 0x000604 pci 0000:00:1c.7: PME# supported from D0 D3hot D3cold pci 0000:00:1c.7: PME# disabled pci 0000:00:1d.0: [8086:1c26] type 0 class 0x000c03 pci 0000:00:1d.0: reg 10: [mem 0xf9622000-0xf96223ff] pci 0000:00:1d.0: PME# supported from D0 D3hot D3cold pci 0000:00:1d.0: PME# disabled pci 0000:00:1f.0: [8086:1c46] type 0 class 0x000601 pci 0000:00:1f.2: [8086:1c02] type 0 class 0x000106 pci 0000:00:1f.2: reg 10: [io 0xf090-0xf097] pci 0000:00:1f.2: reg 14: [io 0xf080-0xf083] pci 0000:00:1f.2: reg 18: [io 0xf070-0xf077] pci 0000:00:1f.2: reg 1c: [io 0xf060-0xf063] pci 0000:00:1f.2: reg 20: [io 0xf020-0xf03f] pci 0000:00:1f.2: reg 24: [mem 0xf9621000-0xf96217ff] pci 0000:00:1f.2: PME# supported from D3hot pci 0000:00:1f.2: PME# disabled pci 0000:00:1f.3: [8086:1c22] type 0 class 0x000c05 pci 0000:00:1f.3: reg 10: [mem 0xf9620000-0xf96200ff 64bit] pci 0000:00:1f.3: reg 20: [io 0xf000-0xf01f] pci 0000:01:00.0: [10de:0142] type 0 class 0x000300 pci 0000:01:00.0: reg 10: [mem 0xf4000000-0xf7ffffff] pci 0000:01:00.0: reg 14: [mem 0xd0000000-0xdfffffff 64bit pref] pci 0000:01:00.0: reg 1c: [mem 0xf8000000-0xf8ffffff 64bit] pci 0000:01:00.0: reg 30: [mem 0xf9000000-0xf901ffff pref] pci 0000:01:00.0: disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force' pci 0000:00:01.0: PCI bridge to [bus 01-01] pci 0000:00:01.0: bridge window [io 0xf000-0x0000] (disabled) pci 0000:00:01.0: bridge window [mem 0xf4000000-0xf90fffff] pci 0000:00:01.0: bridge window [mem 0xd0000000-0xdfffffff 64bit pref] pci 0000:00:1c.0: PCI bridge to [bus 02-02] pci 0000:00:1c.0: bridge window [io 0xf000-0x0000] (disabled) pci 0000:00:1c.0: bridge window [mem 0xfff00000-0x000fffff] (disabled) pci 0000:00:1c.0: bridge window [mem 0xfff00000-0x000fffff pref] (disabled) pci 0000:03:00.0: [1033:0194] type 0 class 0x000c03 pci 0000:03:00.0: reg 10: [mem 0xf9500000-0xf9501fff 64bit] pci 0000:03:00.0: PME# supported from D0 D3hot D3cold pci 0000:03:00.0: PME# disabled pci 0000:00:1c.1: PCI bridge to [bus 03-03] pci 0000:00:1c.1: bridge window [io 0xf000-0x0000] (disabled) pci 0000:00:1c.1: bridge window [mem 0xf9500000-0xf95fffff] pci 0000:00:1c.1: bridge window [mem 0xfff00000-0x000fffff pref] (disabled) pci 0000:00:1c.2: PCI bridge to [bus 04-04] pci 0000:00:1c.2: bridge window [io 0xf000-0x0000] (disabled) pci 0000:00:1c.2: bridge window [mem 0xfff00000-0x000fffff] (disabled) pci 0000:00:1c.2: bridge window [mem 0xfff00000-0x000fffff pref] (disabled) pci 0000:05:00.0: [197b:2362] type 0 class 0x000101 pci 0000:05:00.0: reg 10: [io 0xe040-0xe047] pci 0000:05:00.0: reg 14: [io 0xe030-0xe033] pci 0000:05:00.0: reg 18: [io 0xe020-0xe027] pci 0000:05:00.0: reg 1c: [io 0xe010-0xe013] pci 0000:05:00.0: reg 20: [io 0xe000-0xe00f] pci 0000:05:00.0: reg 24: [mem 0xf9410000-0xf94101ff] pci 0000:05:00.0: reg 30: [mem 0x00000000-0x0000ffff pref] pci 0000:05:00.0: PME# supported from D3hot pci 0000:05:00.0: PME# disabled pci 0000:00:1c.3: PCI bridge to [bus 05-05] pci 0000:00:1c.3: bridge window [io 0xe000-0xefff] pci 0000:00:1c.3: bridge window [mem 0xf9400000-0xf94fffff] pci 0000:00:1c.3: bridge window [mem 0xfff00000-0x000fffff pref] (disabled) pci 0000:06:00.0: [1033:0194] type 0 class 0x000c03 pci 0000:06:00.0: reg 10: [mem 0xf9300000-0xf9301fff 64bit] pci 0000:06:00.0: PME# supported from D0 D3hot D3cold pci 0000:06:00.0: PME# disabled pci 0000:00:1c.4: PCI bridge to [bus 06-06] pci 0000:00:1c.4: bridge window [io 0xf000-0x0000] (disabled) pci 0000:00:1c.4: bridge window [mem 0xf9300000-0xf93fffff] pci 0000:00:1c.4: bridge window [mem 0xfff00000-0x000fffff pref] (disabled) pci 0000:07:00.0: [1b21:1080] type 1 class 0x000604 pci 0000:00:1c.6: PCI bridge to [bus 07-08] (subtractive decode) pci 0000:00:1c.6: bridge window [io 0xd000-0xdfff] pci 0000:00:1c.6: bridge window [mem 0xf9200000-0xf92fffff] pci 0000:00:1c.6: bridge window [mem 0xfff00000-0x000fffff pref] (disabled) pci 0000:00:1c.6: bridge window [io 0x0000-0x0cf7] (subtractive decode) pci 0000:00:1c.6: bridge window [io 0x0d00-0xffff] (subtractive decode) pci 0000:00:1c.6: bridge window [mem 0x000a0000-0x000bffff] (subtractive decode) pci 0000:00:1c.6: bridge window [mem 0x000c8000-0x000dffff] (subtractive decode) pci 0000:00:1c.6: bridge window [mem 0xd0000000-0xffffffff] (subtractive decode) pci 0000:08:01.0: [1102:0002] type 0 class 0x000401 pci 0000:08:01.0: reg 10: [io 0xd080-0xd09f] pci 0000:08:01.0: supports D1 D2 pci 0000:08:01.1: [1102:7002] type 0 class 0x000980 pci 0000:08:01.1: reg 10: [io 0xd0a0-0xd0a7] pci 0000:08:01.1: supports D1 D2 pci 0000:08:03.0: [1106:3044] type 0 class 0x000c00 pci 0000:08:03.0: reg 10: [mem 0xf9200000-0xf92007ff] pci 0000:08:03.0: reg 14: [io 0xd000-0xd07f] pci 0000:08:03.0: supports D2 pci 0000:08:03.0: PME# supported from D2 D3hot D3cold pci 0000:08:03.0: PME# disabled pci 0000:07:00.0: PCI bridge to [bus 08-08] (subtractive decode) pci 0000:07:00.0: bridge window [io 0xd000-0xdfff] pci 0000:07:00.0: bridge window [mem 0xf9200000-0xf92fffff] pci 0000:07:00.0: bridge window [mem 0xfff00000-0x000fffff pref] (disabled) pci 0000:07:00.0: bridge window [io 0xd000-0xdfff] (subtractive decode) pci 0000:07:00.0: bridge window [mem 0xf9200000-0xf92fffff] (subtractive decode) pci 0000:07:00.0: bridge window [??? 0x00000000 flags 0x0] (subtractive decode) pci 0000:07:00.0: bridge window [??? 0x00000000 flags 0x0] (subtractive decode) pci 0000:07:00.0: bridge window [io 0x0000-0x0cf7] (subtractive decode) pci 0000:07:00.0: bridge window [io 0x0d00-0xffff] (subtractive decode) pci 0000:07:00.0: bridge window [mem 0x000a0000-0x000bffff] (subtractive decode) pci 0000:07:00.0: bridge window [mem 0x000c8000-0x000dffff] (subtractive decode) pci 0000:07:00.0: bridge window [mem 0xd0000000-0xffffffff] (subtractive decode) pci 0000:09:00.0: [1b4b:9172] type 0 class 0x000106 pci 0000:09:00.0: reg 10: [io 0xc040-0xc047] pci 0000:09:00.0: reg 14: [io 0xc030-0xc033] pci 0000:09:00.0: reg 18: [io 0xc020-0xc027] pci 0000:09:00.0: reg 1c: [io 0xc010-0xc013] pci 0000:09:00.0: reg 20: [io 0xc000-0xc00f] pci 0000:09:00.0: reg 24: [mem 0xf9110000-0xf91101ff] pci 0000:09:00.0: reg 30: [mem 0xf9100000-0xf910ffff pref] pci 0000:09:00.0: PME# supported from D3hot pci 0000:09:00.0: PME# disabled pci 0000:00:1c.7: PCI bridge to [bus 09-09] pci 0000:00:1c.7: bridge window [io 0xc000-0xcfff] pci 0000:00:1c.7: bridge window [mem 0xf9100000-0xf91fffff] pci 0000:00:1c.7: bridge window [mem 0xfff00000-0x000fffff pref] (disabled) pci_bus 0000:00: on NUMA node 0 ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.P0P1._PRT] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PEX0._PRT] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PEX1._PRT] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PEX2._PRT] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PEX3._PRT] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PEX4._PRT] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PEX6._PRT] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PEX6.BR24._PRT] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PEX7._PRT] pci0000:00: Requesting ACPI _OSC control (0x1d) pci0000:00: ACPI _OSC control (0x1c) granted ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 10 *11 12 14 15) ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 *7 10 11 12 14 15) ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 *5 6 10 11 12 14 15) ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 10 *11 12 14 15) ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 *10 11 12 14 15) ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 *10 11 12 14 15) ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 10 11 12 14 15) *0 ACPI: PCI Interrupt Link [LNKH] (IRQs *3 4 5 6 7 10 11 12 14 15) vgaarb: device added: PCI:0000:01:00.0,decodes=io+mem,owns=io+mem,locks=none vgaarb: loaded SCSI subsystem initialized libata version 3.00 loaded. usbcore: registered new interface driver usbfs usbcore: registered new interface driver hub usbcore: registered new device driver usb Advanced Linux Sound Architecture Driver Version 1.0.24. PCI: Using ACPI for IRQ routing PCI: pci_cache_line_size set to 64 bytes reserve RAM buffer: 000000000009a800 - 000000000009ffff reserve RAM buffer: 00000000cefcf000 - 00000000cfffffff reserve RAM buffer: 00000000cf5cc000 - 00000000cfffffff reserve RAM buffer: 00000000cf800000 - 00000000cfffffff reserve RAM buffer: 000000022f800000 - 000000022fffffff hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0 hpet0: 8 comparators, 64-bit 14.318180 MHz counter Switching to clocksource hpet pnp: PnP ACPI init ACPI: bus type pnp registered pnp 00:00: [bus 00-ff] pnp 00:00: [io 0x0cf8-0x0cff] pnp 00:00: [io 0x0000-0x0cf7 window] pnp 00:00: [io 0x0d00-0xffff window] pnp 00:00: [mem 0x000a0000-0x000bffff window] pnp 00:00: [mem 0x000c8000-0x000dffff window] pnp 00:00: [mem 0xd0000000-0xffffffff window] pnp 00:00: [mem 0x00000000 window] pnp 00:00: Plug and Play ACPI device, IDs PNP0a08 PNP0a03 (active) pnp 00:01: [mem 0xfed10000-0xfed19fff] pnp 00:01: [mem 0xe0000000-0xe3ffffff] pnp 00:01: [mem 0xfed90000-0xfed93fff] pnp 00:01: [mem 0xfed20000-0xfed3ffff] pnp 00:01: [mem 0xfee00000-0xfee0ffff] system 00:01: [mem 0xfed10000-0xfed19fff] has been reserved system 00:01: [mem 0xe0000000-0xe3ffffff] has been reserved system 00:01: [mem 0xfed90000-0xfed93fff] has been reserved Switched to NOHz mode on CPU #0 Switched to NOHz mode on CPU #6 Switched to NOHz mode on CPU #7 Switched to NOHz mode on CPU #1 Switched to NOHz mode on CPU #2 Switched to NOHz mode on CPU #3 Switched to NOHz mode on CPU #4 Switched to NOHz mode on CPU #5 system 00:01: [mem 0xfed20000-0xfed3ffff] has been reserved system 00:01: [mem 0xfee00000-0xfee0ffff] has been reserved system 00:01: Plug and Play ACPI device, IDs PNP0c01 (active) pnp 00:02: [io 0x0000-0xffffffffffffffff disabled] pnp 00:02: [io 0x0000-0xffffffffffffffff disabled] pnp 00:02: [io 0x0290-0x029f] pnp 00:02: [io 0x0000-0xffffffffffffffff disabled] system 00:02: [io 0x0290-0x029f] has been reserved system 00:02: Plug and Play ACPI device, IDs PNP0c02 (active) pnp 00:03: [dma 4] pnp 00:03: [io 0x0000-0x000f] pnp 00:03: [io 0x0081-0x0083] pnp 00:03: [io 0x0087] pnp 00:03: [io 0x0089-0x008b] pnp 00:03: [io 0x008f] pnp 00:03: [io 0x00c0-0x00df] pnp 00:03: Plug and Play ACPI device, IDs PNP0200 (active) pnp 00:04: [io 0x0070-0x0071] pnp 00:04: [irq 8] pnp 00:04: Plug and Play ACPI device, IDs PNP0b00 (active) pnp 00:05: [io 0x0061] pnp 00:05: Plug and Play ACPI device, IDs PNP0800 (active) pnp 00:06: [io 0x0010-0x001f] pnp 00:06: [io 0x0022-0x003f] pnp 00:06: [io 0x0044-0x005f] pnp 00:06: [io 0x0063] pnp 00:06: [io 0x0065] pnp 00:06: [io 0x0067-0x006f] pnp 00:06: [io 0x0072-0x007f] pnp 00:06: [io 0x0080] pnp 00:06: [io 0x0084-0x0086] pnp 00:06: [io 0x0088] pnp 00:06: [io 0x008c-0x008e] pnp 00:06: [io 0x0090-0x009f] pnp 00:06: [io 0x00a2-0x00bf] pnp 00:06: [io 0x00e0-0x00ef] pnp 00:06: [io 0x04d0-0x04d1] system 00:06: [io 0x04d0-0x04d1] has been reserved system 00:06: Plug and Play ACPI device, IDs PNP0c02 (active) pnp 00:07: [io 0x00f0-0x00ff] pnp 00:07: [irq 13] pnp 00:07: Plug and Play ACPI device, IDs PNP0c04 (active) pnp 00:08: [io 0x03f8-0x03ff] pnp 00:08: [irq 4] pnp 00:08: [dma 0 disabled] pnp 00:08: Plug and Play ACPI device, IDs PNP0501 (active) pnp 00:09: [io 0x0400-0x0453] pnp 00:09: [io 0x0458-0x047f] pnp 00:09: [io 0x0000-0xffffffffffffffff disabled] pnp 00:09: [io 0x0500-0x057f] pnp 00:09: [mem 0xfed1c000-0xfed1ffff] pnp 00:09: [mem 0xfec00000-0xfecfffff] pnp 00:09: [mem 0xfed08000-0xfed08fff] pnp 00:09: [mem 0xff000000-0xffffffff] system 00:09: [io 0x0400-0x0453] has been reserved system 00:09: [io 0x0458-0x047f] has been reserved system 00:09: [io 0x0500-0x057f] has been reserved system 00:09: [mem 0xfed1c000-0xfed1ffff] has been reserved system 00:09: [mem 0xfec00000-0xfecfffff] could not be reserved system 00:09: [mem 0xfed08000-0xfed08fff] has been reserved system 00:09: [mem 0xff000000-0xffffffff] has been reserved system 00:09: Plug and Play ACPI device, IDs PNP0c01 (active) pnp 00:0a: [io 0x0454-0x0457] system 00:0a: [io 0x0454-0x0457] has been reserved system 00:0a: Plug and Play ACPI device, IDs INT3f0d PNP0c02 (active) pnp 00:0b: [mem 0xfed00000-0xfed003ff] pnp 00:0b: Plug and Play ACPI device, IDs PNP0103 (active) pnp: PnP ACPI: found 12 devices ACPI: ACPI bus type pnp unregistered pci 0000:00:1c.3: BAR 9: assigned [mem 0xe4000000-0xe40fffff pref] pci 0000:00:01.0: PCI bridge to [bus 01-01] pci 0000:00:01.0: bridge window [io disabled] pci 0000:00:01.0: bridge window [mem 0xf4000000-0xf90fffff] pci 0000:00:01.0: bridge window [mem 0xd0000000-0xdfffffff 64bit pref] pci 0000:00:1c.0: PCI bridge to [bus 02-02] pci 0000:00:1c.0: bridge window [io disabled] pci 0000:00:1c.0: bridge window [mem disabled] pci 0000:00:1c.0: bridge window [mem pref disabled] pci 0000:00:1c.1: PCI bridge to [bus 03-03] pci 0000:00:1c.1: bridge window [io disabled] pci 0000:00:1c.1: bridge window [mem 0xf9500000-0xf95fffff] pci 0000:00:1c.1: bridge window [mem pref disabled] pci 0000:00:1c.2: PCI bridge to [bus 04-04] pci 0000:00:1c.2: bridge window [io disabled] pci 0000:00:1c.2: bridge window [mem disabled] pci 0000:00:1c.2: bridge window [mem pref disabled] pci 0000:05:00.0: BAR 6: assigned [mem 0xe4000000-0xe400ffff pref] pci 0000:00:1c.3: PCI bridge to [bus 05-05] pci 0000:00:1c.3: bridge window [io 0xe000-0xefff] pci 0000:00:1c.3: bridge window [mem 0xf9400000-0xf94fffff] pci 0000:00:1c.3: bridge window [mem 0xe4000000-0xe40fffff pref] pci 0000:00:1c.4: PCI bridge to [bus 06-06] pci 0000:00:1c.4: bridge window [io disabled] pci 0000:00:1c.4: bridge window [mem 0xf9300000-0xf93fffff] pci 0000:00:1c.4: bridge window [mem pref disabled] pci 0000:07:00.0: PCI bridge to [bus 08-08] pci 0000:07:00.0: bridge window [io 0xd000-0xdfff] pci 0000:07:00.0: bridge window [mem 0xf9200000-0xf92fffff] pci 0000:07:00.0: bridge window [mem pref disabled] pci 0000:00:1c.6: PCI bridge to [bus 07-08] pci 0000:00:1c.6: bridge window [io 0xd000-0xdfff] pci 0000:00:1c.6: bridge window [mem 0xf9200000-0xf92fffff] pci 0000:00:1c.6: bridge window [mem pref disabled] pci 0000:00:1c.7: PCI bridge to [bus 09-09] pci 0000:00:1c.7: bridge window [io 0xc000-0xcfff] pci 0000:00:1c.7: bridge window [mem 0xf9100000-0xf91fffff] pci 0000:00:1c.7: bridge window [mem pref disabled] pci 0000:00:01.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16 pci 0000:00:01.0: setting latency timer to 64 pci 0000:00:1c.0: PCI INT A -> GSI 17 (level, low) -> IRQ 17 pci 0000:00:1c.0: setting latency timer to 64 pci 0000:00:1c.1: PCI INT B -> GSI 16 (level, low) -> IRQ 16 pci 0000:00:1c.1: setting latency timer to 64 pci 0000:00:1c.2: PCI INT C -> GSI 18 (level, low) -> IRQ 18 pci 0000:00:1c.2: setting latency timer to 64 pci 0000:00:1c.3: PCI INT D -> GSI 19 (level, low) -> IRQ 19 pci 0000:00:1c.3: setting latency timer to 64 pci 0000:00:1c.4: PCI INT A -> GSI 17 (level, low) -> IRQ 17 pci 0000:00:1c.4: setting latency timer to 64 pci 0000:00:1c.6: PCI INT C -> GSI 18 (level, low) -> IRQ 18 pci 0000:00:1c.6: setting latency timer to 64 pci 0000:07:00.0: PCI INT A -> GSI 18 (level, low) -> IRQ 18 pci 0000:07:00.0: setting latency timer to 64 pci 0000:00:1c.7: PCI INT D -> GSI 19 (level, low) -> IRQ 19 pci 0000:00:1c.7: setting latency timer to 64 pci_bus 0000:00: resource 4 [io 0x0000-0x0cf7] pci_bus 0000:00: resource 5 [io 0x0d00-0xffff] pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff] pci_bus 0000:00: resource 7 [mem 0x000c8000-0x000dffff] pci_bus 0000:00: resource 8 [mem 0xd0000000-0xffffffff] pci_bus 0000:01: resource 1 [mem 0xf4000000-0xf90fffff] pci_bus 0000:01: resource 2 [mem 0xd0000000-0xdfffffff 64bit pref] pci_bus 0000:03: resource 1 [mem 0xf9500000-0xf95fffff] pci_bus 0000:05: resource 0 [io 0xe000-0xefff] pci_bus 0000:05: resource 1 [mem 0xf9400000-0xf94fffff] pci_bus 0000:05: resource 2 [mem 0xe4000000-0xe40fffff pref] pci_bus 0000:06: resource 1 [mem 0xf9300000-0xf93fffff] pci_bus 0000:07: resource 0 [io 0xd000-0xdfff] pci_bus 0000:07: resource 1 [mem 0xf9200000-0xf92fffff] pci_bus 0000:07: resource 4 [io 0x0000-0x0cf7] pci_bus 0000:07: resource 5 [io 0x0d00-0xffff] pci_bus 0000:07: resource 6 [mem 0x000a0000-0x000bffff] pci_bus 0000:07: resource 7 [mem 0x000c8000-0x000dffff] pci_bus 0000:07: resource 8 [mem 0xd0000000-0xffffffff] pci_bus 0000:08: resource 0 [io 0xd000-0xdfff] pci_bus 0000:08: resource 1 [mem 0xf9200000-0xf92fffff] pci_bus 0000:08: resource 4 [io 0xd000-0xdfff] pci_bus 0000:08: resource 5 [mem 0xf9200000-0xf92fffff] pci_bus 0000:08: resource 8 [io 0x0000-0x0cf7] pci_bus 0000:08: resource 9 [io 0x0d00-0xffff] pci_bus 0000:08: resource 10 [mem 0x000a0000-0x000bffff] pci_bus 0000:08: resource 11 [mem 0x000c8000-0x000dffff] pci_bus 0000:08: resource 12 [mem 0xd0000000-0xffffffff] pci_bus 0000:09: resource 0 [io 0xc000-0xcfff] pci_bus 0000:09: resource 1 [mem 0xf9100000-0xf91fffff] NET: Registered protocol family 2 IP route cache hash table entries: 262144 (order: 9, 2097152 bytes) TCP established hash table entries: 262144 (order: 10, 4194304 bytes) TCP bind hash table entries: 65536 (order: 8, 1048576 bytes) TCP: Hash tables configured (established 262144 bind 65536) TCP reno registered UDP hash table entries: 4096 (order: 5, 131072 bytes) UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes) NET: Registered protocol family 1 pci 0000:00:1a.0: EHCI: BIOS handoff pci 0000:00:1d.0: EHCI: BIOS handoff pci 0000:01:00.0: Boot video device PCI: CLS 64 bytes, default 64 PCI-DMA: Using software bounce buffering for IO (SWIOTLB) Placing 64MB software IO TLB between ffff8800cafcf000 - ffff8800cefcf000 software IO TLB at phys 0xcafcf000 - 0xcefcf000 microcode: CPU0 sig=0x206a7, pf=0x2, revision=0x14 microcode: CPU1 sig=0x206a7, pf=0x2, revision=0x14 microcode: CPU2 sig=0x206a7, pf=0x2, revision=0x14 microcode: CPU3 sig=0x206a7, pf=0x2, revision=0x14 microcode: CPU4 sig=0x206a7, pf=0x2, revision=0x14 microcode: CPU5 sig=0x206a7, pf=0x2, revision=0x14 microcode: CPU6 sig=0x206a7, pf=0x2, revision=0x14 microcode: CPU7 sig=0x206a7, pf=0x2, revision=0x14 microcode: Microcode Update Driver: v2.00 , Peter Oruba fuse init (API version 7.16) SGI XFS with ACLs, security attributes, large block/inode numbers, no debug enabled msgmni has been set to 15934 NET: Registered protocol family 38 Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253) io scheduler noop registered io scheduler cfq registered (default) pcieport 0000:00:01.0: setting latency timer to 64 pcieport 0000:00:01.0: irq 40 for MSI/MSI-X pcieport 0000:00:1c.0: setting latency timer to 64 pcieport 0000:00:1c.0: irq 41 for MSI/MSI-X pcieport 0000:00:1c.1: setting latency timer to 64 pcieport 0000:00:1c.1: irq 42 for MSI/MSI-X pcieport 0000:00:1c.2: setting latency timer to 64 pcieport 0000:00:1c.2: irq 43 for MSI/MSI-X pcieport 0000:00:1c.3: setting latency timer to 64 pcieport 0000:00:1c.3: irq 44 for MSI/MSI-X pcieport 0000:00:1c.4: setting latency timer to 64 pcieport 0000:00:1c.4: irq 45 for MSI/MSI-X pcieport 0000:00:1c.7: setting latency timer to 64 pcieport 0000:00:1c.7: irq 46 for MSI/MSI-X pcieport 0000:00:01.0: Signaling PME through PCIe PME interrupt pci 0000:01:00.0: Signaling PME through PCIe PME interrupt pcie_pme 0000:00:01.0:pcie01: service driver pcie_pme loaded pcieport 0000:00:1c.0: Signaling PME through PCIe PME interrupt pcie_pme 0000:00:1c.0:pcie01: service driver pcie_pme loaded pcieport 0000:00:1c.1: Signaling PME through PCIe PME interrupt pci 0000:03:00.0: Signaling PME through PCIe PME interrupt pcie_pme 0000:00:1c.1:pcie01: service driver pcie_pme loaded pcieport 0000:00:1c.2: Signaling PME through PCIe PME interrupt pcie_pme 0000:00:1c.2:pcie01: service driver pcie_pme loaded pcieport 0000:00:1c.3: Signaling PME through PCIe PME interrupt pci 0000:05:00.0: Signaling PME through PCIe PME interrupt pcie_pme 0000:00:1c.3:pcie01: service driver pcie_pme loaded pcieport 0000:00:1c.4: Signaling PME through PCIe PME interrupt pci 0000:06:00.0: Signaling PME through PCIe PME interrupt pcie_pme 0000:00:1c.4:pcie01: service driver pcie_pme loaded pcieport 0000:00:1c.7: Signaling PME through PCIe PME interrupt pci 0000:09:00.0: Signaling PME through PCIe PME interrupt pcie_pme 0000:00:1c.7:pcie01: service driver pcie_pme loaded intel_idle: MWAIT substates: 0x1120 intel_idle: v0.4 model 0x2A intel_idle: lapic_timer_reliable_states 0xffffffff input: Power Button as /devices/LNXSYSTM:00/device:00/PNP0C0C:00/input/input0 ACPI: Power Button [PWRB] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input1 ACPI: Power Button [PWRF] ACPI: acpi_idle yielding to intel_idle [drm] Initialized drm 1.1.0 20060810 brd: module loaded loop: module loaded ahci 0000:00:1f.2: version 3.0 ahci 0000:00:1f.2: PCI INT B -> GSI 20 (level, low) -> IRQ 20 ahci 0000:00:1f.2: irq 47 for MSI/MSI-X ahci 0000:00:1f.2: AHCI 0001.0300 32 slots 6 ports 6 Gbps 0x3f impl SATA mode ahci 0000:00:1f.2: flags: 64bit ncq sntf pm led clo pio slum part ems apst ahci 0000:00:1f.2: setting latency timer to 64 scsi0 : ahci scsi1 : ahci scsi2 : ahci scsi3 : ahci scsi4 : ahci scsi5 : ahci ata1: SATA max UDMA/133 abar m2048@0xf9621000 port 0xf9621100 irq 47 ata2: SATA max UDMA/133 abar m2048@0xf9621000 port 0xf9621180 irq 47 ata3: SATA max UDMA/133 abar m2048@0xf9621000 port 0xf9621200 irq 47 ata4: SATA max UDMA/133 abar m2048@0xf9621000 port 0xf9621280 irq 47 ata5: SATA max UDMA/133 abar m2048@0xf9621000 port 0xf9621300 irq 47 ata6: SATA max UDMA/133 abar m2048@0xf9621000 port 0xf9621380 irq 47 ahci 0000:05:00.0: PCI INT A -> GSI 19 (level, low) -> IRQ 19 ahci 0000:05:00.0: AHCI 0001.0100 32 slots 2 ports 3 Gbps 0x3 impl SATA mode ahci 0000:05:00.0: flags: 64bit ncq pm led clo pmp pio slum part ahci 0000:05:00.0: setting latency timer to 64 scsi6 : ahci scsi7 : ahci ata7: SATA max UDMA/133 abar m512@0xf9410000 port 0xf9410100 irq 19 ata8: SATA max UDMA/133 abar m512@0xf9410000 port 0xf9410180 irq 19 ahci 0000:09:00.0: PCI INT A -> GSI 19 (level, low) -> IRQ 19 ahci 0000:09:00.0: irq 48 for MSI/MSI-X ahci 0000:09:00.0: AHCI 0001.0000 32 slots 2 ports 6 Gbps 0x3 impl SATA mode ahci 0000:09:00.0: flags: 64bit ncq sntf led only pmp fbs pio slum part sxs ahci 0000:09:00.0: setting latency timer to 64 scsi8 : ahci scsi9 : ahci ata9: SATA max UDMA/133 abar m512@0xf9110000 port 0xf9110100 irq 48 ata10: SATA max UDMA/133 abar m512@0xf9110000 port 0xf9110180 irq 48 e1000e: Intel(R) PRO/1000 Network Driver - 1.3.10-k2 e1000e: Copyright(c) 1999 - 2011 Intel Corporation. e1000e 0000:00:19.0: PCI INT A -> GSI 18 (level, low) -> IRQ 18 e1000e 0000:00:19.0: setting latency timer to 64 e1000e 0000:00:19.0: irq 49 for MSI/MSI-X e1000e 0000:00:19.0: eth0: (PCI Express:2.5GB/s:Width x1) bc:ae:c5:77:ec:75 e1000e 0000:00:19.0: eth0: Intel(R) PRO/1000 Network Connection e1000e 0000:00:19.0: eth0: MAC: 10, PHY: 11, PBA No: FFFFFF-0FF ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver ehci_hcd: block sizes: qh 104 qtd 96 itd 192 sitd 96 ehci_hcd 0000:00:1a.0: PCI INT A -> GSI 23 (level, low) -> IRQ 23 ehci_hcd 0000:00:1a.0: setting latency timer to 64 ehci_hcd 0000:00:1a.0: EHCI Host Controller drivers/usb/core/inode.c: creating file 'devices' drivers/usb/core/inode.c: creating file '001' ehci_hcd 0000:00:1a.0: new USB bus registered, assigned bus number 1 ehci_hcd 0000:00:1a.0: reset hcs_params 0x200002 dbg=2 cc=0 pcc=0 ordered !ppc ports=2 ehci_hcd 0000:00:1a.0: reset hcc_params 36881 caching frame 1024 64 bit addr ehci_hcd 0000:00:1a.0: support lpm ehci_hcd 0000:00:1a.0: debug port 2 ehci_hcd 0000:00:1a.0: reset command 0080002 (park)=0 ithresh=8 period=1024 Reset HALT ehci_hcd 0000:00:1a.0: cache line size of 64 is not supported ehci_hcd 0000:00:1a.0: supports USB remote wakeup ehci_hcd 0000:00:1a.0: irq 23, io mem 0xf9623000 ehci_hcd 0000:00:1a.0: reset command 0080002 (park)=0 ithresh=8 period=1024 Reset HALT ehci_hcd 0000:00:1a.0: init command 0010001 (park)=0 ithresh=1 period=1024 RUN ehci_hcd 0000:00:1a.0: USB 2.0 started, EHCI 1.00 usb usb1: default language 0x0409 usb usb1: udev 1, busnum 1, minor = 0 usb usb1: New USB device found, idVendor=1d6b, idProduct=0002 usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1 usb usb1: Product: EHCI Host Controller usb usb1: Manufacturer: Linux 2.6.39-rc7+ ehci_hcd usb usb1: SerialNumber: 0000:00:1a.0 usb usb1: usb_probe_device usb usb1: configuration #1 chosen from 1 choice usb usb1: adding 1-0:1.0 (config #1, interface 0) hub 1-0:1.0: usb_probe_interface hub 1-0:1.0: usb_probe_interface - got id hub 1-0:1.0: USB hub found hub 1-0:1.0: 2 ports detected hub 1-0:1.0: standalone hub hub 1-0:1.0: no power switching (usb 1.0) hub 1-0:1.0: individual port over-current protection hub 1-0:1.0: power on to power good time: 20ms hub 1-0:1.0: local power source is good hub 1-0:1.0: trying to enable port power on non-switchable hub drivers/usb/core/inode.c: creating file '001' ehci_hcd 0000:00:1d.0: PCI INT A -> GSI 23 (level, low) -> IRQ 23 ehci_hcd 0000:00:1d.0: setting latency timer to 64 ehci_hcd 0000:00:1d.0: EHCI Host Controller drivers/usb/core/inode.c: creating file '002' ehci_hcd 0000:00:1d.0: new USB bus registered, assigned bus number 2 ehci_hcd 0000:00:1d.0: reset hcs_params 0x200002 dbg=2 cc=0 pcc=0 ordered !ppc ports=2 ehci_hcd 0000:00:1d.0: reset hcc_params 36881 caching frame 1024 64 bit addr ehci_hcd 0000:00:1d.0: support lpm ehci_hcd 0000:00:1d.0: debug port 2 ehci_hcd 0000:00:1d.0: reset command 0080002 (park)=0 ithresh=8 period=1024 Reset HALT ehci_hcd 0000:00:1d.0: cache line size of 64 is not supported ehci_hcd 0000:00:1d.0: supports USB remote wakeup ehci_hcd 0000:00:1d.0: irq 23, io mem 0xf9622000 ehci_hcd 0000:00:1d.0: reset command 0080002 (park)=0 ithresh=8 period=1024 Reset HALT ehci_hcd 0000:00:1d.0: init command 0010001 (park)=0 ithresh=1 period=1024 RUN ehci_hcd 0000:00:1d.0: USB 2.0 started, EHCI 1.00 usb usb2: default language 0x0409 usb usb2: udev 1, busnum 2, minor = 128 usb usb2: New USB device found, idVendor=1d6b, idProduct=0002 usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1 usb usb2: Product: EHCI Host Controller usb usb2: Manufacturer: Linux 2.6.39-rc7+ ehci_hcd usb usb2: SerialNumber: 0000:00:1d.0 usb usb2: usb_probe_device usb usb2: configuration #1 chosen from 1 choice usb usb2: adding 2-0:1.0 (config #1, interface 0) hub 2-0:1.0: usb_probe_interface hub 2-0:1.0: usb_probe_interface - got id hub 2-0:1.0: USB hub found hub 2-0:1.0: 2 ports detected hub 2-0:1.0: standalone hub hub 2-0:1.0: no power switching (usb 1.0) hub 2-0:1.0: individual port over-current protection hub 2-0:1.0: power on to power good time: 20ms hub 2-0:1.0: local power source is good hub 2-0:1.0: trying to enable port power on non-switchable hub drivers/usb/core/inode.c: creating file '001' ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver ohci_hcd: block sizes: ed 80 td 96 xhci_hcd 0000:03:00.0: PCI INT A -> GSI 17 (level, low) -> IRQ 17 xhci_hcd 0000:03:00.0: setting latency timer to 64 xhci_hcd 0000:03:00.0: xHCI Host Controller drivers/usb/core/inode.c: creating file '003' xhci_hcd 0000:03:00.0: new USB bus registered, assigned bus number 3 xhci_hcd 0000:03:00.0: xHCI capability registers at ffffc9000003c000: xhci_hcd 0000:03:00.0: CAPLENGTH AND HCIVERSION 0x960020: xhci_hcd 0000:03:00.0: CAPLENGTH: 0x20 xhci_hcd 0000:03:00.0: HCIVERSION: 0x96 xhci_hcd 0000:03:00.0: HCSPARAMS 1: 0x4000820 xhci_hcd 0000:03:00.0: Max device slots: 32 xhci_hcd 0000:03:00.0: Max interrupters: 8 xhci_hcd 0000:03:00.0: Max ports: 4 xhci_hcd 0000:03:00.0: HCSPARAMS 2: 0x11 xhci_hcd 0000:03:00.0: Isoc scheduling threshold: 1 xhci_hcd 0000:03:00.0: Maximum allowed segments in event ring: 1 xhci_hcd 0000:03:00.0: HCSPARAMS 3 0x0: xhci_hcd 0000:03:00.0: Worst case U1 device exit latency: 0 xhci_hcd 0000:03:00.0: Worst case U2 device exit latency: 0 xhci_hcd 0000:03:00.0: HCC PARAMS 0x14042cb: xhci_hcd 0000:03:00.0: HC generates 64 bit addresses xhci_hcd 0000:03:00.0: FIXME: more HCCPARAMS debugging xhci_hcd 0000:03:00.0: RTSOFF 0x600: xhci_hcd 0000:03:00.0: xHCI operational registers at ffffc9000003c020: xhci_hcd 0000:03:00.0: USBCMD 0x0: xhci_hcd 0000:03:00.0: HC is being stopped xhci_hcd 0000:03:00.0: HC has finished hard reset xhci_hcd 0000:03:00.0: Event Interrupts disabled xhci_hcd 0000:03:00.0: Host System Error Interrupts disabled xhci_hcd 0000:03:00.0: HC has finished light reset xhci_hcd 0000:03:00.0: USBSTS 0x1: xhci_hcd 0000:03:00.0: Event ring is empty xhci_hcd 0000:03:00.0: No Host System Error xhci_hcd 0000:03:00.0: HC is halted xhci_hcd 0000:03:00.0: ffffc9000003c420 port status reg = 0x2a0 xhci_hcd 0000:03:00.0: ffffc9000003c424 port power reg = 0x0 xhci_hcd 0000:03:00.0: ffffc9000003c428 port link reg = 0x0 xhci_hcd 0000:03:00.0: ffffc9000003c42c port reserved reg = 0x0 xhci_hcd 0000:03:00.0: ffffc9000003c430 port status reg = 0x2a0 xhci_hcd 0000:03:00.0: ffffc9000003c434 port power reg = 0x0 xhci_hcd 0000:03:00.0: ffffc9000003c438 port link reg = 0x0 xhci_hcd 0000:03:00.0: ffffc9000003c43c port reserved reg = 0x0 xhci_hcd 0000:03:00.0: ffffc9000003c440 port status reg = 0x2a0 xhci_hcd 0000:03:00.0: ffffc9000003c444 port power reg = 0x0 xhci_hcd 0000:03:00.0: ffffc9000003c448 port link reg = 0x0 xhci_hcd 0000:03:00.0: ffffc9000003c44c port reserved reg = 0x0 xhci_hcd 0000:03:00.0: ffffc9000003c450 port status reg = 0x2a0 xhci_hcd 0000:03:00.0: ffffc9000003c454 port power reg = 0x0 xhci_hcd 0000:03:00.0: ffffc9000003c458 port link reg = 0x0 xhci_hcd 0000:03:00.0: ffffc9000003c45c port reserved reg = 0x0 xhci_hcd 0000:03:00.0: // Halt the HC xhci_hcd 0000:03:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc9000003c020, 32'h0, 4'hf); xhci_hcd 0000:03:00.0: Resetting HCD xhci_hcd 0000:03:00.0: // Reset the HC xhci_hcd 0000:03:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc9000003c020, 32'h2, 4'hf); xhci_hcd 0000:03:00.0: Wait for controller to be ready for doorbell rings xhci_hcd 0000:03:00.0: Reset complete xhci_hcd 0000:03:00.0: Enabling 64-bit DMA addresses. xhci_hcd 0000:03:00.0: Calling HCD init xhci_hcd 0000:03:00.0: xhci_init xhci_hcd 0000:03:00.0: xHCI doesn't need link TRB QUIRK xhci_hcd 0000:03:00.0: Supported page size register = 0x1 xhci_hcd 0000:03:00.0: Supported page size of 4K xhci_hcd 0000:03:00.0: HCD page size set to 4K xhci_hcd 0000:03:00.0: // xHC can handle at most 32 device slots. xhci_hcd 0000:03:00.0: // Setting Max device slots reg = 0x20. xhci_hcd 0000:03:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc9000003c058, 32'h20, 4'hf); xhci_hcd 0000:03:00.0: // Device context base array address = 0xca806000 (DMA), ffff8800ca806000 (virt) xhci_hcd 0000:03:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc9000003c050, 64'hca806000, 4'hf); xhci_hcd 0000:03:00.0: Allocating ring at ffff88022e5b59c0 xhci_hcd 0000:03:00.0: Allocating priv segment structure at ffff88022d577000 xhci_hcd 0000:03:00.0: // Allocating segment at ffff8800ca807000 (virtual) 0xca807000 (DMA) xhci_hcd 0000:03:00.0: Linking segment 0xca807000 to segment 0xca807000 (DMA) xhci_hcd 0000:03:00.0: Wrote link toggle flag to segment ffff88022d577000 (virtual), 0xca807000 (DMA) xhci_hcd 0000:03:00.0: Allocated command ring at ffff88022e5b59c0 xhci_hcd 0000:03:00.0: First segment DMA is 0xca807000 xhci_hcd 0000:03:00.0: // Setting command ring address to 0x20 xhci_hcd 0000:03:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc9000003c038, 64'hca807001, 4'hf); xhci_hcd 0000:03:00.0: // xHC command ring deq ptr low bits + flags = @00000000 xhci_hcd 0000:03:00.0: // xHC command ring deq ptr high bits = @00000000 xhci_hcd 0000:03:00.0: // Doorbell array is located at offset 0x800 from cap regs base addr xhci_hcd 0000:03:00.0: // xHCI capability registers at ffffc9000003c000: xhci_hcd 0000:03:00.0: // @ffffc9000003c000 = 0x960020 (CAPLENGTH AND HCIVERSION) xhci_hcd 0000:03:00.0: // CAPLENGTH: 0x20 xhci_hcd 0000:03:00.0: // xHCI operational registers at ffffc9000003c020: xhci_hcd 0000:03:00.0: // @ffffc9000003c018 = 0x600 RTSOFF xhci_hcd 0000:03:00.0: // xHCI runtime registers at ffffc9000003c600: xhci_hcd 0000:03:00.0: // @ffffc9000003c014 = 0x800 DBOFF xhci_hcd 0000:03:00.0: // Doorbell array at ffffc9000003c800: xhci_hcd 0000:03:00.0: xHCI runtime registers at ffffc9000003c600: xhci_hcd 0000:03:00.0: ffffc9000003c600: Microframe index = 0x0 xhci_hcd 0000:03:00.0: // Allocating event ring xhci_hcd 0000:03:00.0: Allocating ring at ffff88022e5b5a20 xhci_hcd 0000:03:00.0: Allocating priv segment structure at ffff88022d577020 xhci_hcd 0000:03:00.0: // Allocating segment at ffff8800ca807400 (virtual) 0xca807400 (DMA) xhci_hcd 0000:03:00.0: Linking segment 0xca807400 to segment 0xca807400 (DMA) xhci_hcd 0000:03:00.0: TRB math tests passed. xhci_hcd 0000:03:00.0: // Allocated event ring segment table at 0xca808000 xhci_hcd 0000:03:00.0: Set ERST to 0; private num segs = 1, virt addr = ffff8800ca808000, dma addr = 0xca808000 xhci_hcd 0000:03:00.0: // Write ERST size = 1 to ir_set 0 (some bits preserved) xhci_hcd 0000:03:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc9000003c628, 32'h1, 4'hf); xhci_hcd 0000:03:00.0: // Set ERST entries to point to event ring. xhci_hcd 0000:03:00.0: // Set ERST base address for ir_set 0 = 0xca808000 xhci_hcd 0000:03:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc9000003c630, 64'hca808000, 4'hf); xhci_hcd 0000:03:00.0: // Write event ring dequeue pointer, preserving EHB bit xhci_hcd 0000:03:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc9000003c638, 64'hca807400, 4'hf); xhci_hcd 0000:03:00.0: Wrote ERST address to ir_set 0. xhci_hcd 0000:03:00.0: Allocating 0 scratchpad buffers xhci_hcd 0000:03:00.0: Ext Cap ffffc9000003c510, port offset = 1, count = 2, revision = 0x3 xhci_hcd 0000:03:00.0: Ext Cap ffffc9000003c520, port offset = 3, count = 2, revision = 0x2 xhci_hcd 0000:03:00.0: Found 2 USB 2.0 ports and 2 USB 3.0 ports. xhci_hcd 0000:03:00.0: USB 2.0 port at index 2, addr = ffffc9000003c440 xhci_hcd 0000:03:00.0: USB 2.0 port at index 3, addr = ffffc9000003c450 xhci_hcd 0000:03:00.0: USB 3.0 port at index 0, addr = ffffc9000003c420 xhci_hcd 0000:03:00.0: USB 3.0 port at index 1, addr = ffffc9000003c430 xhci_hcd 0000:03:00.0: Finished xhci_init xhci_hcd 0000:03:00.0: Called HCD init xhci_hcd 0000:03:00.0: Got SBRN 48 xhci_hcd 0000:03:00.0: MWI active xhci_hcd 0000:03:00.0: Finished xhci_pci_reinit xhci_hcd 0000:03:00.0: supports USB remote wakeup xhci_hcd 0000:03:00.0: irq 17, io mem 0xf9500000 xhci_hcd 0000:03:00.0: xhci_run xhci_hcd 0000:03:00.0: irq 50 for MSI/MSI-X xhci_hcd 0000:03:00.0: irq 51 for MSI/MSI-X xhci_hcd 0000:03:00.0: irq 52 for MSI/MSI-X xhci_hcd 0000:03:00.0: irq 53 for MSI/MSI-X xhci_hcd 0000:03:00.0: irq 54 for MSI/MSI-X xhci_hcd 0000:03:00.0: irq 55 for MSI/MSI-X xhci_hcd 0000:03:00.0: irq 56 for MSI/MSI-X xhci_hcd 0000:03:00.0: irq 57 for MSI/MSI-X xhci_hcd 0000:03:00.0: Setting event ring polling timer xhci_hcd 0000:03:00.0: Command ring memory map follows: xhci_hcd 0000:03:00.0: @ca807000 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807010 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807020 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807030 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807040 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807050 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807060 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807070 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807080 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807090 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8070a0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8070b0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8070c0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8070d0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8070e0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8070f0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807100 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807110 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807120 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807130 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807140 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807150 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807160 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807170 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807180 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807190 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8071a0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8071b0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8071c0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8071d0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8071e0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8071f0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807200 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807210 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807220 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807230 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807240 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807250 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807260 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807270 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807280 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807290 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8072a0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8072b0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8072c0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8072d0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8072e0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8072f0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807300 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807310 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807320 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807330 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807340 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807350 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807360 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807370 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807380 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807390 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8073a0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8073b0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8073c0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8073d0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8073e0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8073f0 ca807000 00000000 00000000 00001802 xhci_hcd 0000:03:00.0: Ring has not been updated xhci_hcd 0000:03:00.0: Ring deq = ffff8800ca807000 (virt), 0xca807000 (dma) xhci_hcd 0000:03:00.0: Ring deq updated 0 times xhci_hcd 0000:03:00.0: Ring enq = ffff8800ca807000 (virt), 0xca807000 (dma) xhci_hcd 0000:03:00.0: Ring enq updated 0 times xhci_hcd 0000:03:00.0: // xHC command ring deq ptr low bits + flags = @00000000 xhci_hcd 0000:03:00.0: // xHC command ring deq ptr high bits = @00000000 xhci_hcd 0000:03:00.0: ERST memory map follows: xhci_hcd 0000:03:00.0: @ca808000 ca807400 00000000 00000040 00000000 xhci_hcd 0000:03:00.0: Event ring: xhci_hcd 0000:03:00.0: @ca807400 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807410 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807420 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807430 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807440 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807450 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807460 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807470 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807480 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807490 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8074a0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8074b0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8074c0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8074d0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8074e0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8074f0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807500 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807510 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807520 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807530 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807540 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807550 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807560 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807570 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807580 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807590 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8075a0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8075b0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8075c0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8075d0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8075e0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8075f0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807600 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807610 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807620 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807630 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807640 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807650 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807660 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807670 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807680 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807690 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8076a0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8076b0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8076c0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8076d0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8076e0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8076f0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807700 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807710 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807720 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807730 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807740 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807750 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807760 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807770 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807780 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807790 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8077a0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8077b0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8077c0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8077d0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8077e0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8077f0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: Ring has not been updated xhci_hcd 0000:03:00.0: Ring deq = ffff8800ca807400 (virt), 0xca807400 (dma) xhci_hcd 0000:03:00.0: Ring deq updated 0 times xhci_hcd 0000:03:00.0: Ring enq = ffff8800ca807400 (virt), 0xca807400 (dma) xhci_hcd 0000:03:00.0: Ring enq updated 0 times xhci_hcd 0000:03:00.0: ERST deq = 64'hca807400 xhci_hcd 0000:03:00.0: // Set the interrupt modulation register xhci_hcd 0000:03:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc9000003c624, 32'ha0, 4'hf); xhci_hcd 0000:03:00.0: // Enable interrupts, cmd = 0x4. xhci_hcd 0000:03:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc9000003c020, 32'h4, 4'hf); xhci_hcd 0000:03:00.0: // Enabling event ring interrupter ffffc9000003c620 by writing 0x2 to irq_pending xhci_hcd 0000:03:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc9000003c620, 32'h2, 4'hf); xhci_hcd 0000:03:00.0: ffffc9000003c620: ir_set[0] xhci_hcd 0000:03:00.0: ffffc9000003c620: ir_set.pending = 0x2 xhci_hcd 0000:03:00.0: ffffc9000003c624: ir_set.control = 0xa0 xhci_hcd 0000:03:00.0: ffffc9000003c628: ir_set.erst_size = 0x1 xhci_hcd 0000:03:00.0: ffffc9000003c630: ir_set.erst_base = @ca808000 xhci_hcd 0000:03:00.0: ffffc9000003c638: ir_set.erst_dequeue = @ca807400 xhci_hcd 0000:03:00.0: Endpoint state = 0x1 xhci_hcd 0000:03:00.0: Command ring enq = 0xca807010 (DMA) xhci_hcd 0000:03:00.0: Finished xhci_run for USB2 roothub usb usb3: default language 0x0409 usb usb3: udev 1, busnum 3, minor = 256 usb usb3: New USB device found, idVendor=1d6b, idProduct=0002 usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1 usb usb3: Product: xHCI Host Controller usb usb3: Manufacturer: Linux 2.6.39-rc7+ xhci_hcd usb usb3: SerialNumber: 0000:03:00.0 usb usb3: usb_probe_device usb usb3: configuration #1 chosen from 1 choice xHCI xhci_add_endpoint called for root hub xHCI xhci_check_bandwidth called for root hub usb usb3: adding 3-0:1.0 (config #1, interface 0) hub 3-0:1.0: usb_probe_interface hub 3-0:1.0: usb_probe_interface - got id hub 3-0:1.0: USB hub found hub 3-0:1.0: 2 ports detected hub 3-0:1.0: standalone hub hub 3-0:1.0: individual port power switching hub 3-0:1.0: individual port over-current protection hub 3-0:1.0: Single TT hub 3-0:1.0: TT requires at most 8 FS bit times (666 ns) hub 3-0:1.0: power on to power good time: 20ms hub 3-0:1.0: local power source is good hub 3-0:1.0: enabling power on all ports xhci_hcd 0000:03:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc9000003c440, 32'h2a0, 4'hf); xhci_hcd 0000:03:00.0: set port power, actual port 0 status = 0x2a0 xhci_hcd 0000:03:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc9000003c450, 32'h2a0, 4'hf); xhci_hcd 0000:03:00.0: set port power, actual port 1 status = 0x2a0 drivers/usb/core/inode.c: creating file '001' xhci_hcd 0000:03:00.0: xHCI Host Controller drivers/usb/core/inode.c: creating file '004' xhci_hcd 0000:03:00.0: new USB bus registered, assigned bus number 4 xhci_hcd 0000:03:00.0: Enabling 64-bit DMA addresses. xhci_hcd 0000:03:00.0: supports USB remote wakeup xhci_hcd 0000:03:00.0: // Turn on HC, cmd = 0x5. xhci_hcd 0000:03:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc9000003c020, 32'h5, 4'hf); xhci_hcd 0000:03:00.0: // Ding dong! xhci_hcd 0000:03:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc9000003c800, 32'h0, 4'hf); xhci_hcd 0000:03:00.0: Finished xhci_run for USB3 roothub usb usb4: skipped 1 descriptor after endpoint usb usb4: default language 0x0409 usb usb4: udev 1, busnum 4, minor = 384 usb usb4: New USB device found, idVendor=1d6b, idProduct=0003 xhci_hcd 0000:03:00.0: op reg status = 00000008 xhci_hcd 0000:03:00.0: Event ring dequeue ptr: xhci_hcd 0000:03:00.0: @ca807400 ca807000 00000000 01004015 0000c001 xhci_hcd 0000:03:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc9000003c024, 32'h8, 4'hf); xhci_hcd 0000:03:00.0: In xhci_handle_event xhci_hcd 0000:03:00.0: xhci_handle_event - OS owns TRB xhci_hcd 0000:03:00.0: Vendor specific event TRB type = 48 xhci_hcd 0000:03:00.0: NEC firmware version 40.15 xhci_hcd 0000:03:00.0: Command ring deq = 0xca807010 (DMA) xhci_hcd 0000:03:00.0: Event ring deq = 0xca807410 (DMA) xhci_hcd 0000:03:00.0: In xhci_handle_event xhci_hcd 0000:03:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc9000003c638, 64'hca807418, 4'hf); usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1 usb usb4: Product: xHCI Host Controller usb usb4: Manufacturer: Linux 2.6.39-rc7+ xhci_hcd usb usb4: SerialNumber: 0000:03:00.0 usb usb4: usb_probe_device usb usb4: configuration #1 chosen from 1 choice xHCI xhci_add_endpoint called for root hub xHCI xhci_check_bandwidth called for root hub usb usb4: adding 4-0:1.0 (config #1, interface 0) hub 4-0:1.0: usb_probe_interface hub 4-0:1.0: usb_probe_interface - got id hub 4-0:1.0: USB hub found hub 4-0:1.0: 2 ports detected hub 4-0:1.0: standalone hub hub 4-0:1.0: individual port power switching hub 4-0:1.0: individual port over-current protection hub 4-0:1.0: TT requires at most 8 FS bit times (666 ns) hub 4-0:1.0: power on to power good time: 20ms hub 4-0:1.0: local power source is good hub 4-0:1.0: enabling power on all ports xhci_hcd 0000:03:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc9000003c420, 32'h2a0, 4'hf); xhci_hcd 0000:03:00.0: set port power, actual port 0 status = 0x2a0 xhci_hcd 0000:03:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc9000003c430, 32'h2a0, 4'hf); xhci_hcd 0000:03:00.0: set port power, actual port 1 status = 0x2a0 drivers/usb/core/inode.c: creating file '001' xhci_hcd 0000:06:00.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16 xhci_hcd 0000:06:00.0: setting latency timer to 64 xhci_hcd 0000:06:00.0: xHCI Host Controller drivers/usb/core/inode.c: creating file '005' xhci_hcd 0000:06:00.0: new USB bus registered, assigned bus number 5 xhci_hcd 0000:06:00.0: xHCI capability registers at ffffc90000068000: xhci_hcd 0000:06:00.0: CAPLENGTH AND HCIVERSION 0x960020: xhci_hcd 0000:06:00.0: CAPLENGTH: 0x20 xhci_hcd 0000:06:00.0: HCIVERSION: 0x96 xhci_hcd 0000:06:00.0: HCSPARAMS 1: 0x4000820 xhci_hcd 0000:06:00.0: Max device slots: 32 xhci_hcd 0000:06:00.0: Max interrupters: 8 xhci_hcd 0000:06:00.0: Max ports: 4 xhci_hcd 0000:06:00.0: HCSPARAMS 2: 0x11 xhci_hcd 0000:06:00.0: Isoc scheduling threshold: 1 xhci_hcd 0000:06:00.0: Maximum allowed segments in event ring: 1 xhci_hcd 0000:06:00.0: HCSPARAMS 3 0x0: xhci_hcd 0000:06:00.0: Worst case U1 device exit latency: 0 xhci_hcd 0000:06:00.0: Worst case U2 device exit latency: 0 xhci_hcd 0000:06:00.0: HCC PARAMS 0x14042cb: xhci_hcd 0000:06:00.0: HC generates 64 bit addresses xhci_hcd 0000:06:00.0: FIXME: more HCCPARAMS debugging xhci_hcd 0000:06:00.0: RTSOFF 0x600: xhci_hcd 0000:06:00.0: xHCI operational registers at ffffc90000068020: xhci_hcd 0000:06:00.0: USBCMD 0x0: xhci_hcd 0000:06:00.0: HC is being stopped xhci_hcd 0000:06:00.0: HC has finished hard reset xhci_hcd 0000:06:00.0: Event Interrupts disabled xhci_hcd 0000:06:00.0: Host System Error Interrupts disabled xhci_hcd 0000:06:00.0: HC has finished light reset xhci_hcd 0000:06:00.0: USBSTS 0x1: xhci_hcd 0000:06:00.0: Event ring is empty xhci_hcd 0000:06:00.0: No Host System Error xhci_hcd 0000:06:00.0: HC is halted xhci_hcd 0000:06:00.0: ffffc90000068420 port status reg = 0x2a0 xhci_hcd 0000:06:00.0: ffffc90000068424 port power reg = 0x0 xhci_hcd 0000:06:00.0: ffffc90000068428 port link reg = 0x0 xhci_hcd 0000:06:00.0: ffffc9000006842c port reserved reg = 0x0 xhci_hcd 0000:06:00.0: ffffc90000068430 port status reg = 0x2a0 xhci_hcd 0000:06:00.0: ffffc90000068434 port power reg = 0x0 xhci_hcd 0000:06:00.0: ffffc90000068438 port link reg = 0x0 xhci_hcd 0000:06:00.0: ffffc9000006843c port reserved reg = 0x0 xhci_hcd 0000:06:00.0: ffffc90000068440 port status reg = 0x2a0 xhci_hcd 0000:06:00.0: ffffc90000068444 port power reg = 0x0 xhci_hcd 0000:06:00.0: ffffc90000068448 port link reg = 0x0 xhci_hcd 0000:06:00.0: ffffc9000006844c port reserved reg = 0x0 xhci_hcd 0000:06:00.0: ffffc90000068450 port status reg = 0x2a0 xhci_hcd 0000:06:00.0: ffffc90000068454 port power reg = 0x0 xhci_hcd 0000:06:00.0: ffffc90000068458 port link reg = 0x0 xhci_hcd 0000:06:00.0: ffffc9000006845c port reserved reg = 0x0 xhci_hcd 0000:06:00.0: // Halt the HC xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068020, 32'h0, 4'hf); xhci_hcd 0000:06:00.0: Resetting HCD xhci_hcd 0000:06:00.0: // Reset the HC xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068020, 32'h2, 4'hf); xhci_hcd 0000:06:00.0: Wait for controller to be ready for doorbell rings xhci_hcd 0000:06:00.0: Reset complete xhci_hcd 0000:06:00.0: Enabling 64-bit DMA addresses. xhci_hcd 0000:06:00.0: Calling HCD init xhci_hcd 0000:06:00.0: xhci_init xhci_hcd 0000:06:00.0: xHCI doesn't need link TRB QUIRK xhci_hcd 0000:06:00.0: Supported page size register = 0x1 xhci_hcd 0000:06:00.0: Supported page size of 4K xhci_hcd 0000:06:00.0: HCD page size set to 4K xhci_hcd 0000:06:00.0: // xHC can handle at most 32 device slots. xhci_hcd 0000:06:00.0: // Setting Max device slots reg = 0x20. xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068058, 32'h20, 4'hf); xhci_hcd 0000:06:00.0: // Device context base array address = 0xca809000 (DMA), ffff8800ca809000 (virt) xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90000068050, 64'hca809000, 4'hf); xhci_hcd 0000:06:00.0: Allocating ring at ffff88022e5b5ae0 xhci_hcd 0000:06:00.0: Allocating priv segment structure at ffff88022d577120 xhci_hcd 0000:06:00.0: // Allocating segment at ffff8800ca80a000 (virtual) 0xca80a000 (DMA) xhci_hcd 0000:06:00.0: Linking segment 0xca80a000 to segment 0xca80a000 (DMA) xhci_hcd 0000:06:00.0: Wrote link toggle flag to segment ffff88022d577120 (virtual), 0xca80a000 (DMA) xhci_hcd 0000:06:00.0: Allocated command ring at ffff88022e5b5ae0 xhci_hcd 0000:06:00.0: First segment DMA is 0xca80a000 xhci_hcd 0000:06:00.0: // Setting command ring address to 0x20 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90000068038, 64'hca80a001, 4'hf); xhci_hcd 0000:06:00.0: // xHC command ring deq ptr low bits + flags = @00000000 xhci_hcd 0000:06:00.0: // xHC command ring deq ptr high bits = @00000000 xhci_hcd 0000:06:00.0: // Doorbell array is located at offset 0x800 from cap regs base addr xhci_hcd 0000:06:00.0: // xHCI capability registers at ffffc90000068000: xhci_hcd 0000:06:00.0: // @ffffc90000068000 = 0x960020 (CAPLENGTH AND HCIVERSION) xhci_hcd 0000:06:00.0: // CAPLENGTH: 0x20 xhci_hcd 0000:06:00.0: // xHCI operational registers at ffffc90000068020: xhci_hcd 0000:06:00.0: // @ffffc90000068018 = 0x600 RTSOFF xhci_hcd 0000:06:00.0: // xHCI runtime registers at ffffc90000068600: xhci_hcd 0000:06:00.0: // @ffffc90000068014 = 0x800 DBOFF xhci_hcd 0000:06:00.0: // Doorbell array at ffffc90000068800: xhci_hcd 0000:06:00.0: xHCI runtime registers at ffffc90000068600: xhci_hcd 0000:06:00.0: ffffc90000068600: Microframe index = 0x0 xhci_hcd 0000:06:00.0: // Allocating event ring xhci_hcd 0000:06:00.0: Allocating ring at ffff88022e5b5b40 xhci_hcd 0000:06:00.0: Allocating priv segment structure at ffff88022d577140 xhci_hcd 0000:06:00.0: // Allocating segment at ffff8800ca80a400 (virtual) 0xca80a400 (DMA) xhci_hcd 0000:06:00.0: Linking segment 0xca80a400 to segment 0xca80a400 (DMA) xhci_hcd 0000:06:00.0: TRB math tests passed. xhci_hcd 0000:06:00.0: // Allocated event ring segment table at 0xca80b000 xhci_hcd 0000:06:00.0: Set ERST to 0; private num segs = 1, virt addr = ffff8800ca80b000, dma addr = 0xca80b000 xhci_hcd 0000:06:00.0: // Write ERST size = 1 to ir_set 0 (some bits preserved) xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068628, 32'h1, 4'hf); xhci_hcd 0000:06:00.0: // Set ERST entries to point to event ring. xhci_hcd 0000:06:00.0: // Set ERST base address for ir_set 0 = 0xca80b000 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90000068630, 64'hca80b000, 4'hf); xhci_hcd 0000:06:00.0: // Write event ring dequeue pointer, preserving EHB bit xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90000068638, 64'hca80a400, 4'hf); xhci_hcd 0000:06:00.0: Wrote ERST address to ir_set 0. xhci_hcd 0000:06:00.0: Allocating 0 scratchpad buffers xhci_hcd 0000:06:00.0: Ext Cap ffffc90000068510, port offset = 1, count = 2, revision = 0x3 xhci_hcd 0000:06:00.0: Ext Cap ffffc90000068520, port offset = 3, count = 2, revision = 0x2 xhci_hcd 0000:06:00.0: Found 2 USB 2.0 ports and 2 USB 3.0 ports. xhci_hcd 0000:06:00.0: USB 2.0 port at index 2, addr = ffffc90000068440 xhci_hcd 0000:06:00.0: USB 2.0 port at index 3, addr = ffffc90000068450 xhci_hcd 0000:06:00.0: USB 3.0 port at index 0, addr = ffffc90000068420 xhci_hcd 0000:06:00.0: USB 3.0 port at index 1, addr = ffffc90000068430 xhci_hcd 0000:06:00.0: Finished xhci_init xhci_hcd 0000:06:00.0: Called HCD init xhci_hcd 0000:06:00.0: Got SBRN 48 xhci_hcd 0000:06:00.0: MWI active xhci_hcd 0000:06:00.0: Finished xhci_pci_reinit xhci_hcd 0000:06:00.0: supports USB remote wakeup xhci_hcd 0000:06:00.0: irq 16, io mem 0xf9300000 xhci_hcd 0000:06:00.0: xhci_run xhci_hcd 0000:06:00.0: irq 58 for MSI/MSI-X xhci_hcd 0000:06:00.0: irq 59 for MSI/MSI-X xhci_hcd 0000:06:00.0: irq 60 for MSI/MSI-X xhci_hcd 0000:06:00.0: irq 61 for MSI/MSI-X xhci_hcd 0000:06:00.0: irq 62 for MSI/MSI-X xhci_hcd 0000:06:00.0: irq 63 for MSI/MSI-X xhci_hcd 0000:06:00.0: irq 64 for MSI/MSI-X xhci_hcd 0000:06:00.0: irq 65 for MSI/MSI-X xhci_hcd 0000:06:00.0: Setting event ring polling timer xhci_hcd 0000:06:00.0: Command ring memory map follows: xhci_hcd 0000:06:00.0: @ca80a000 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a010 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a020 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a030 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a040 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a050 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a060 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a070 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a080 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a090 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a0a0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a0b0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a0c0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a0d0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a0e0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a0f0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a100 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a110 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a120 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a130 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a140 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a150 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a160 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a170 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a180 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a190 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a1a0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a1b0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a1c0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a1d0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a1e0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a1f0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a200 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a210 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a220 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a230 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a240 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a250 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a260 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a270 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a280 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a290 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a2a0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a2b0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a2c0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a2d0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a2e0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a2f0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a300 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a310 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a320 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a330 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a340 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a350 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a360 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a370 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a380 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a390 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a3a0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a3b0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a3c0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a3d0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a3e0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a3f0 ca80a000 00000000 00000000 00001802 xhci_hcd 0000:06:00.0: Ring has not been updated xhci_hcd 0000:06:00.0: Ring deq = ffff8800ca80a000 (virt), 0xca80a000 (dma) xhci_hcd 0000:06:00.0: Ring deq updated 0 times xhci_hcd 0000:06:00.0: Ring enq = ffff8800ca80a000 (virt), 0xca80a000 (dma) xhci_hcd 0000:06:00.0: Ring enq updated 0 times xhci_hcd 0000:06:00.0: // xHC command ring deq ptr low bits + flags = @00000000 xhci_hcd 0000:06:00.0: // xHC command ring deq ptr high bits = @00000000 xhci_hcd 0000:06:00.0: ERST memory map follows: xhci_hcd 0000:06:00.0: @ca80b000 ca80a400 00000000 00000040 00000000 xhci_hcd 0000:06:00.0: Event ring: xhci_hcd 0000:06:00.0: @ca80a400 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a410 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a420 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a430 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a440 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a450 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a460 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a470 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a480 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a490 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a4a0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a4b0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a4c0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a4d0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a4e0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a4f0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a500 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a510 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a520 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a530 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a540 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a550 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a560 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a570 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a580 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a590 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a5a0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a5b0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a5c0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a5d0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a5e0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a5f0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a600 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a610 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a620 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a630 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a640 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a650 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a660 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a670 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a680 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a690 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a6a0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a6b0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a6c0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a6d0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a6e0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a6f0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a700 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a710 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a720 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a730 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a740 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a750 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a760 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a770 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a780 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a790 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a7a0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a7b0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a7c0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a7d0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a7e0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a7f0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: Ring has not been updated xhci_hcd 0000:06:00.0: Ring deq = ffff8800ca80a400 (virt), 0xca80a400 (dma) xhci_hcd 0000:06:00.0: Ring deq updated 0 times xhci_hcd 0000:06:00.0: Ring enq = ffff8800ca80a400 (virt), 0xca80a400 (dma) xhci_hcd 0000:06:00.0: Ring enq updated 0 times xhci_hcd 0000:06:00.0: ERST deq = 64'hca80a400 xhci_hcd 0000:06:00.0: // Set the interrupt modulation register xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068624, 32'ha0, 4'hf); xhci_hcd 0000:06:00.0: // Enable interrupts, cmd = 0x4. xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068020, 32'h4, 4'hf); xhci_hcd 0000:06:00.0: // Enabling event ring interrupter ffffc90000068620 by writing 0x2 to irq_pending xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068620, 32'h2, 4'hf); xhci_hcd 0000:06:00.0: ffffc90000068620: ir_set[0] xhci_hcd 0000:06:00.0: ffffc90000068620: ir_set.pending = 0x2 xhci_hcd 0000:06:00.0: ffffc90000068624: ir_set.control = 0xa0 xhci_hcd 0000:06:00.0: ffffc90000068628: ir_set.erst_size = 0x1 xhci_hcd 0000:06:00.0: ffffc90000068630: ir_set.erst_base = @ca80b000 xhci_hcd 0000:06:00.0: ffffc90000068638: ir_set.erst_dequeue = @ca80a400 xhci_hcd 0000:06:00.0: Endpoint state = 0x1 xhci_hcd 0000:06:00.0: Command ring enq = 0xca80a010 (DMA) xhci_hcd 0000:06:00.0: Finished xhci_run for USB2 roothub usb usb5: default language 0x0409 usb usb5: udev 1, busnum 5, minor = 512 usb usb5: New USB device found, idVendor=1d6b, idProduct=0002 usb usb5: New USB device strings: Mfr=3, Product=2, SerialNumber=1 usb usb5: Product: xHCI Host Controller usb usb5: Manufacturer: Linux 2.6.39-rc7+ xhci_hcd usb usb5: SerialNumber: 0000:06:00.0 usb usb5: usb_probe_device usb usb5: configuration #1 chosen from 1 choice xHCI xhci_add_endpoint called for root hub xHCI xhci_check_bandwidth called for root hub usb usb5: adding 5-0:1.0 (config #1, interface 0) hub 5-0:1.0: usb_probe_interface hub 5-0:1.0: usb_probe_interface - got id hub 5-0:1.0: USB hub found hub 5-0:1.0: 2 ports detected hub 5-0:1.0: standalone hub hub 5-0:1.0: individual port power switching hub 5-0:1.0: individual port over-current protection hub 5-0:1.0: Single TT hub 5-0:1.0: TT requires at most 8 FS bit times (666 ns) hub 5-0:1.0: power on to power good time: 20ms hub 5-0:1.0: local power source is good hub 5-0:1.0: enabling power on all ports xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068440, 32'h2a0, 4'hf); xhci_hcd 0000:06:00.0: set port power, actual port 0 status = 0x2a0 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068450, 32'h2a0, 4'hf); xhci_hcd 0000:06:00.0: set port power, actual port 1 status = 0x2a0 drivers/usb/core/inode.c: creating file '001' xhci_hcd 0000:06:00.0: xHCI Host Controller drivers/usb/core/inode.c: creating file '006' xhci_hcd 0000:06:00.0: new USB bus registered, assigned bus number 6 xhci_hcd 0000:06:00.0: Enabling 64-bit DMA addresses. xhci_hcd 0000:06:00.0: supports USB remote wakeup xhci_hcd 0000:06:00.0: // Turn on HC, cmd = 0x5. xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068020, 32'h5, 4'hf); xhci_hcd 0000:06:00.0: // Ding dong! xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068800, 32'h0, 4'hf); xhci_hcd 0000:06:00.0: Finished xhci_run for USB3 roothub usb usb6: skipped 1 descriptor after endpoint usb usb6: default language 0x0409 usb usb6: udev 1, busnum 6, minor = 640 usb usb6: New USB device found, idVendor=1d6b, idProduct=0003 usb usb6: New USB device strings: Mfr=3, Product=2, SerialNumber=1 xhci_hcd 0000:06:00.0: op reg status = 00000008 xhci_hcd 0000:06:00.0: Event ring dequeue ptr: xhci_hcd 0000:06:00.0: @ca80a400 ca80a000 00000000 01004015 0000c001 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068024, 32'h8, 4'hf); xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: xhci_handle_event - OS owns TRB xhci_hcd 0000:06:00.0: Vendor specific event TRB type = 48 xhci_hcd 0000:06:00.0: NEC firmware version 40.15 xhci_hcd 0000:06:00.0: Command ring deq = 0xca80a010 (DMA) xhci_hcd 0000:06:00.0: Event ring deq = 0xca80a410 (DMA) xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90000068638, 64'hca80a418, 4'hf); usb usb6: Product: xHCI Host Controller usb usb6: Manufacturer: Linux 2.6.39-rc7+ xhci_hcd usb usb6: SerialNumber: 0000:06:00.0 usb usb6: usb_probe_device usb usb6: configuration #1 chosen from 1 choice xHCI xhci_add_endpoint called for root hub xHCI xhci_check_bandwidth called for root hub usb usb6: adding 6-0:1.0 (config #1, interface 0) hub 6-0:1.0: usb_probe_interface hub 6-0:1.0: usb_probe_interface - got id hub 6-0:1.0: USB hub found hub 6-0:1.0: 2 ports detected hub 6-0:1.0: standalone hub hub 6-0:1.0: individual port power switching hub 6-0:1.0: individual port over-current protection hub 6-0:1.0: TT requires at most 8 FS bit times (666 ns) hub 6-0:1.0: power on to power good time: 20ms hub 6-0:1.0: local power source is good hub 6-0:1.0: enabling power on all ports xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068420, 32'h2a0, 4'hf); xhci_hcd 0000:06:00.0: set port power, actual port 0 status = 0x2a0 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068430, 32'h2a0, 4'hf); xhci_hcd 0000:06:00.0: set port power, actual port 1 status = 0x2a0 drivers/usb/core/inode.c: creating file '001' i8042: PNP: No PS/2 controller found. Probing ports directly. serio: i8042 KBD port at 0x60,0x64 irq 1 serio: i8042 AUX port at 0x60,0x64 irq 12 mousedev: PS/2 mouse device common for all mice rtc_cmos 00:04: RTC can wake from S4 rtc_cmos 00:04: rtc core: registered rtc_cmos as rtc0 rtc0: alarms up to one month, y3k, 114 bytes nvram, hpet irqs i2c /dev entries driver i801_smbus 0000:00:1f.3: PCI INT C -> GSI 18 (level, low) -> IRQ 18 coretemp coretemp.0: TjMax is 98 C. coretemp coretemp.1: TjMax is 98 C. coretemp coretemp.2: TjMax is 98 C. coretemp coretemp.3: TjMax is 98 C. w83627ehf: Found NCT6776F chip at 0x290 device-mapper: ioctl: 4.20.0-ioctl (2011-02-02) initialised: dm-devel@redhat.com cpuidle: using governor ladder cpuidle: using governor menu usbcore: registered new interface driver usbhid usbhid: USB HID core driver EMU10K1_Audigy 0000:08:01.0: PCI INT A -> GSI 19 (level, low) -> IRQ 19 ata3: SATA link up 3.0 Gbps (SStatus 123 SControl 300) ata6: SATA link up 3.0 Gbps (SStatus 123 SControl 300) ata2: SATA link up 3.0 Gbps (SStatus 123 SControl 300) ata5: SATA link up 3.0 Gbps (SStatus 123 SControl 300) ata4: SATA link up 1.5 Gbps (SStatus 113 SControl 300) ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300) ata7: SATA link down (SStatus 0 SControl 300) ata8: SATA link down (SStatus 0 SControl 300) ata9: SATA link up 3.0 Gbps (SStatus 123 SControl 300) ata10: SATA link down (SStatus 0 SControl 300) ata9.00: ATA-8: INTEL SSDSA2CT040G3, 4PC10302, max UDMA/133 ata9.00: 78165360 sectors, multi 1: LBA48 NCQ (depth 31/32) ata4.00: ATA-7: Maxtor 6L250S0, BACE1G20, max UDMA/133 ata4.00: 490234752 sectors, multi 0: LBA48 NCQ (depth 31/32) ata9.00: configured for UDMA/133 ata1.00: ATA-8: WDC WD20EARS-00MVWB0, 51.0AB51, max UDMA/133 ata1.00: 3907029168 sectors, multi 16: LBA48 NCQ (depth 31/32), AA ata4.00: configured for UDMA/133 ata3.00: ATA-7: SAMSUNG HD103SI, 1AG01118, max UDMA7 ata3.00: 1953525168 sectors, multi 16: LBA48 NCQ (depth 31/32), AA ata2.00: ATA-8: WDC WD20EARS-00J2GB0, 80.00A80, max UDMA/133 ata2.00: 3907029168 sectors, multi 16: LBA48 NCQ (depth 31/32), AA ata1.00: configured for UDMA/133 scsi 0:0:0:0: Direct-Access ATA WDC WD20EARS-00M 51.0 PQ: 0 ANSI: 5 sd 0:0:0:0: [sda] 3907029168 512-byte logical blocks: (2.00 TB/1.81 TiB) sd 0:0:0:0: Attached scsi generic sg0 type 0 sd 0:0:0:0: [sda] Write Protect is off sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00 sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA ata2.00: configured for UDMA/133 scsi 1:0:0:0: Direct-Access ATA WDC WD20EARS-00J 80.0 PQ: 0 ANSI: 5 ata3.00: configured for UDMA/133 sd 1:0:0:0: [sdb] 3907029168 512-byte logical blocks: (2.00 TB/1.81 TiB) sd 1:0:0:0: Attached scsi generic sg1 type 0 sd 1:0:0:0: [sdb] Write Protect is off sd 1:0:0:0: [sdb] Mode Sense: 00 3a 00 00 sd 1:0:0:0: [sdb] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA scsi 2:0:0:0: Direct-Access ATA SAMSUNG HD103SI 1AG0 PQ: 0 ANSI: 5 sd 2:0:0:0: [sdc] 1953525168 512-byte logical blocks: (1.00 TB/931 GiB) sd 2:0:0:0: Attached scsi generic sg2 type 0 scsi 3:0:0:0: Direct-Access ATA Maxtor 6L250S0 BACE PQ: 0 ANSI: 5 sd 2:0:0:0: [sdc] Write Protect is off sd 2:0:0:0: [sdc] Mode Sense: 00 3a 00 00 sd 2:0:0:0: [sdc] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA sd 3:0:0:0: [sdd] 490234752 512-byte logical blocks: (251 GB/233 GiB) sd 3:0:0:0: Attached scsi generic sg3 type 0 sd 3:0:0:0: [sdd] Write Protect is off sd 3:0:0:0: [sdd] Mode Sense: 00 3a 00 00 sd 3:0:0:0: [sdd] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA sdc: unknown partition table sd 2:0:0:0: [sdc] Attached SCSI disk ALSA device list: #0: SB Live! Value [CT4832] (rev.7, serial:0x80271102) at 0xd080, irq 19 Netfilter messages via NETLINK v0.30. nf_conntrack version 0.5.0 (16384 buckets, 65536 max) ctnetlink v0.93: registering with nfnetlink. TCP cubic registered Initializing XFRM netlink socket NET: Registered protocol family 17 NET: Registered protocol family 15 registered taskstats version 1 ata5.00: ATA-7: WDC WD7500AAKS-00RBA0, 30.04G30, max UDMA/133 ata5.00: 1465149168 sectors, multi 16: LBA48 NCQ (depth 31/32), AA rtc_cmos 00:04: setting system clock to 2011-05-13 18:52:13 UTC (1305312733) ata5.00: configured for UDMA/133 scsi 4:0:0:0: Direct-Access ATA WDC WD7500AAKS-0 30.0 PQ: 0 ANSI: 5 sd 4:0:0:0: [sde] 1465149168 512-byte logical blocks: (750 GB/698 GiB) sd 4:0:0:0: [sde] Write Protect is off sd 4:0:0:0: Attached scsi generic sg4 type 0 sd 4:0:0:0: [sde] Mode Sense: 00 3a 00 00 sd 4:0:0:0: [sde] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA ata6.00: ATA-8: ST31000528AS, CC34, max UDMA/133 ata6.00: 1953525168 sectors, multi 16: LBA48 NCQ (depth 31/32) sde: sde1 sde2 < sde5 > sd 4:0:0:0: [sde] Attached SCSI disk sdd: unknown partition table sd 3:0:0:0: [sdd] Attached SCSI disk sdb: unknown partition table sd 1:0:0:0: [sdb] Attached SCSI disk sda: sda1 sda2 < sda5 sda6 sda7 > sd 0:0:0:0: [sda] Attached SCSI disk ehci_hcd 0000:00:1a.0: GetStatus port:1 status 001803 0 ACK POWER sig=j CSC CONNECT hub 1-0:1.0: port 1: status 0501 change 0001 ata6.00: configured for UDMA/133 scsi 5:0:0:0: Direct-Access ATA ST31000528AS CC34 PQ: 0 ANSI: 5 sd 5:0:0:0: [sdf] 1953525168 512-byte logical blocks: (1.00 TB/931 GiB) sd 5:0:0:0: Attached scsi generic sg5 type 0 scsi 8:0:0:0: Direct-Access ATA INTEL SSDSA2CT04 4PC1 PQ: 0 ANSI: 5 sd 5:0:0:0: [sdf] Write Protect is off sd 5:0:0:0: [sdf] Mode Sense: 00 3a 00 00 sd 5:0:0:0: [sdf] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA sd 8:0:0:0: [sdg] 78165360 512-byte logical blocks: (40.0 GB/37.2 GiB) sd 8:0:0:0: Attached scsi generic sg6 type 0 sd 8:0:0:0: [sdg] Write Protect is off sd 8:0:0:0: [sdg] Mode Sense: 00 3a 00 00 sd 8:0:0:0: [sdg] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA sdg: sdg1 sdg2 < sdg5 sdg6 > sd 8:0:0:0: [sdg] Attached SCSI disk ehci_hcd 0000:00:1d.0: GetStatus port:1 status 001803 0 ACK POWER sig=j CSC CONNECT hub 2-0:1.0: port 1: status 0501 change 0001 xhci_hcd 0000:03:00.0: get port status, actual port 0 status = 0x2a0 xhci_hcd 0000:03:00.0: Get port status returned 0x100 xhci_hcd 0000:03:00.0: get port status, actual port 1 status = 0x2a0 xhci_hcd 0000:03:00.0: Get port status returned 0x100 hub 3-0:1.0: state 7 ports 2 chg 0000 evt 0000 xhci_hcd 0000:03:00.0: get port status, actual port 0 status = 0x2a0 xhci_hcd 0000:03:00.0: Get port status returned 0x100 xhci_hcd 0000:03:00.0: get port status, actual port 1 status = 0x2a0 xhci_hcd 0000:03:00.0: Get port status returned 0x100 hub 4-0:1.0: state 7 ports 2 chg 0000 evt 0000 xhci_hcd 0000:06:00.0: get port status, actual port 0 status = 0x2a0 xhci_hcd 0000:06:00.0: Get port status returned 0x100 xhci_hcd 0000:06:00.0: get port status, actual port 1 status = 0x2a0 xhci_hcd 0000:06:00.0: Get port status returned 0x100 hub 5-0:1.0: state 7 ports 2 chg 0000 evt 0000 sdf: unknown partition table sd 5:0:0:0: [sdf] Attached SCSI disk xhci_hcd 0000:06:00.0: get port status, actual port 0 status = 0x2a0 xhci_hcd 0000:06:00.0: Get port status returned 0x100 xhci_hcd 0000:06:00.0: get port status, actual port 1 status = 0x2a0 xhci_hcd 0000:06:00.0: Get port status returned 0x100 hub 6-0:1.0: state 7 ports 2 chg 0000 evt 0000 EXT4-fs (sdg6): mounted filesystem with ordered data mode. Opts: (null) VFS: Mounted root (ext2 filesystem) readonly on device 8:102. Freeing unused kernel memory: 484k freed Write protecting the kernel read-only data: 8192k Freeing unused kernel memory: 1244k freed Freeing unused kernel memory: 196k freed hub 1-0:1.0: state 7 ports 2 chg 0002 evt 0000 hub 1-0:1.0: port 1, status 0501, change 0000, 480 Mb/s ehci_hcd 0000:00:1a.0: port 1 high speed ehci_hcd 0000:00:1a.0: GetStatus port:1 status 001005 0 ACK POWER sig=se0 PE CONNECT usb 1-1: new high speed USB device number 2 using ehci_hcd ehci_hcd 0000:00:1a.0: port 1 high speed ehci_hcd 0000:00:1a.0: GetStatus port:1 status 001005 0 ACK POWER sig=se0 PE CONNECT ehci_hcd 0000:00:1a.0: set dev address 2 for port 1 ehci_hcd 0000:00:1a.0: LPM: no device attached usb 1-1: udev 2, busnum 1, minor = 1 usb 1-1: New USB device found, idVendor=8087, idProduct=0024 usb 1-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0 usb 1-1: usb_probe_device usb 1-1: configuration #1 chosen from 1 choice usb 1-1: adding 1-1:1.0 (config #1, interface 0) hub 1-1:1.0: usb_probe_interface hub 1-1:1.0: usb_probe_interface - got id hub 1-1:1.0: USB hub found hub 1-1:1.0: 6 ports detected hub 1-1:1.0: standalone hub hub 1-1:1.0: individual port power switching hub 1-1:1.0: individual port over-current protection hub 1-1:1.0: Single TT hub 1-1:1.0: TT requires at most 8 FS bit times (666 ns) hub 1-1:1.0: power on to power good time: 100ms hub 1-1:1.0: local power source is good hub 1-1:1.0: enabling power on all ports drivers/usb/core/inode.c: creating file '002' hub 2-0:1.0: state 7 ports 2 chg 0002 evt 0000 hub 2-0:1.0: port 1, status 0501, change 0000, 480 Mb/s ehci_hcd 0000:00:1d.0: port 1 high speed ehci_hcd 0000:00:1d.0: GetStatus port:1 status 001005 0 ACK POWER sig=se0 PE CONNECT usb 1-1: link qh256-0001/ffff88022e596d00 start 1 [1/0 us] usb 2-1: new high speed USB device number 2 using ehci_hcd ehci_hcd 0000:00:1d.0: port 1 high speed ehci_hcd 0000:00:1d.0: GetStatus port:1 status 001005 0 ACK POWER sig=se0 PE CONNECT ehci_hcd 0000:00:1d.0: set dev address 2 for port 1 ehci_hcd 0000:00:1d.0: LPM: no device attached usb 2-1: udev 2, busnum 2, minor = 129 usb 2-1: New USB device found, idVendor=8087, idProduct=0024 usb 2-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0 usb 2-1: usb_probe_device usb 2-1: configuration #1 chosen from 1 choice usb 2-1: adding 2-1:1.0 (config #1, interface 0) hub 2-1:1.0: usb_probe_interface hub 2-1:1.0: usb_probe_interface - got id hub 2-1:1.0: USB hub found hub 2-1:1.0: 8 ports detected hub 2-1:1.0: standalone hub hub 2-1:1.0: individual port power switching hub 2-1:1.0: individual port over-current protection hub 2-1:1.0: Single TT hub 2-1:1.0: TT requires at most 8 FS bit times (666 ns) hub 2-1:1.0: power on to power good time: 100ms hub 2-1:1.0: local power source is good hub 2-1:1.0: enabling power on all ports drivers/usb/core/inode.c: creating file '002' hub 1-1:1.0: state 7 ports 6 chg 0000 evt 0000 udev: starting version 151 udevd (4317): /proc/4317/oom_adj is deprecated, please use /proc/4317/oom_score_adj instead. Refined TSC clocksource calibration: 3400.024 MHz. Switching to clocksource tsc hub 2-1:1.0: port 2: status 0101 change 0001 hub 2-1:1.0: port 5: status 0101 change 0001 hub 2-1:1.0: port 7: status 0101 change 0001 nvidia: module license 'NVIDIA' taints kernel. Disabling lock debugging due to kernel taint usb 2-1: link qh256-0001/ffff88022b9b6a00 start 1 [1/0 us] hub 2-1:1.0: state 7 ports 8 chg 00a4 evt 0000 hub 2-1:1.0: port 2, status 0101, change 0000, 12 Mb/s hub 2-1:1.0: port 2 not reset yet, waiting 10ms usb 2-1.2: new high speed USB device number 3 using ehci_hcd hub 2-1:1.0: port 2 not reset yet, waiting 10ms usb 2-1.2: default language 0x0409 usb 2-1.2: udev 3, busnum 2, minor = 130 usb 2-1.2: New USB device found, idVendor=1a40, idProduct=0101 usb 2-1.2: New USB device strings: Mfr=0, Product=1, SerialNumber=0 usb 2-1.2: Product: USB 2.0 Hub usb 2-1.2: usb_probe_device usb 2-1.2: configuration #1 chosen from 1 choice usb 2-1.2: adding 2-1.2:1.0 (config #1, interface 0) hub 2-1.2:1.0: usb_probe_interface hub 2-1.2:1.0: usb_probe_interface - got id hub 2-1.2:1.0: USB hub found hub 2-1.2:1.0: 4 ports detected hub 2-1.2:1.0: standalone hub hub 2-1.2:1.0: ganged power switching hub 2-1.2:1.0: global over-current protection hub 2-1.2:1.0: Single TT hub 2-1.2:1.0: TT requires at most 8 FS bit times (666 ns) hub 2-1.2:1.0: power on to power good time: 100ms hub 2-1.2:1.0: local power source is good hub 2-1.2:1.0: no over-current condition exists hub 2-1.2:1.0: enabling power on all ports drivers/usb/core/inode.c: creating file '003' hub 2-1:1.0: port 5, status 0101, change 0000, 12 Mb/s hub 2-1:1.0: port 5 not reset yet, waiting 10ms usb 2-1.5: new low speed USB device number 4 using ehci_hcd hub 2-1:1.0: port 5 not reset yet, waiting 10ms hub 2-1.2:1.0: port 3: status 0301 change 0001 nvidia 0000:01:00.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16 nvidia 0000:01:00.0: setting latency timer to 64 vgaarb: device changed decodes: PCI:0000:01:00.0,olddecodes=io+mem,decodes=none:owns=io+mem NVRM: loading NVIDIA UNIX x86_64 Kernel Module 270.41.03 Sat Apr 9 00:06:19 PDT 2011 usb 2-1.5: skipped 1 descriptor after interface usb 2-1.5: skipped 1 descriptor after interface usb 2-1.5: default language 0x0409 usb 2-1.5: udev 4, busnum 2, minor = 131 usb 2-1.5: New USB device found, idVendor=045e, idProduct=00db usb 2-1.5: New USB device strings: Mfr=1, Product=2, SerialNumber=0 usb 2-1.5: Product: Natural® Ergonomic Keyboard 4000 usb 2-1.5: Manufacturer: Microsoft usb 2-1.5: usb_probe_device usb 2-1.5: configuration #1 chosen from 1 choice usb 2-1.5: adding 2-1.5:1.0 (config #1, interface 0) usbhid 2-1.5:1.0: usb_probe_interface usbhid 2-1.5:1.0: usb_probe_interface - got id input: Microsoft Natural® Ergonomic Keyboard 4000 as /devices/pci0000:00/0000:00:1d.0/usb2/2-1/2-1.5/2-1.5:1.0/input/input2 usb 2-1.5: link qh8-0601/ffff88022b9b6500 start 2 [1/2 us] microsoft 0003:045E:00DB.0001: input: USB HID v1.11 Keyboard [Microsoft Natural® Ergonomic Keyboard 4000] on usb-0000:00:1d.0-1.5/input0 usb 2-1.5: adding 2-1.5:1.1 (config #1, interface 1) usbhid 2-1.5:1.1: usb_probe_interface usbhid 2-1.5:1.1: usb_probe_interface - got id usb 2-1.2: link qh256-0001/ffff88022b12e880 start 3 [1/0 us] input: Microsoft Natural® Ergonomic Keyboard 4000 as /devices/pci0000:00/0000:00:1d.0/usb2/2-1/2-1.5/2-1.5:1.1/input/input3 usb 2-1.5: link qh8-0601/ffff88022b9b6300 start 4 [1/2 us] microsoft 0003:045E:00DB.0002: input: USB HID v1.11 Device [Microsoft Natural® Ergonomic Keyboard 4000] on usb-0000:00:1d.0-1.5/input1 drivers/usb/core/inode.c: creating file '004' hub 2-1:1.0: port 7, status 0101, change 0000, 12 Mb/s hub 2-1:1.0: port 7 not reset yet, waiting 10ms usb 2-1.7: new full speed USB device number 5 using ehci_hcd hub 2-1:1.0: port 7 not reset yet, waiting 10ms usb 2-1.7: udev 5, busnum 2, minor = 132 usb 2-1.7: New USB device found, idVendor=0cf3, idProduct=3000 usb 2-1.7: New USB device strings: Mfr=0, Product=0, SerialNumber=0 usb 2-1.7: usb_probe_device usb 2-1.7: configuration #1 chosen from 1 choice usb 2-1.7: adding 2-1.7:1.0 (config #1, interface 0) drivers/usb/core/inode.c: creating file '005' hub 2-1:1.0: state 7 ports 8 chg 0000 evt fe80 hub 2-1.2:1.0: state 7 ports 4 chg 0008 evt 0000 hub 2-1.2:1.0: port 3, status 0301, change 0000, 1.5 Mb/s usb 2-1.2.3: new low speed USB device number 6 using ehci_hcd usb 2-1.2.3: skipped 1 descriptor after interface usb 2-1.2.3: default language 0x0409 usb 2-1.2.3: udev 6, busnum 2, minor = 133 usb 2-1.2.3: New USB device found, idVendor=0583, idProduct=2060 usb 2-1.2.3: New USB device strings: Mfr=0, Product=2, SerialNumber=0 usb 2-1.2.3: Product: USB,2-axis 8-button gamepad usb 2-1.2.3: usb_probe_device usb 2-1.2.3: configuration #1 chosen from 1 choice usb 2-1.2.3: adding 2-1.2.3:1.0 (config #1, interface 0) usbhid 2-1.2.3:1.0: usb_probe_interface usbhid 2-1.2.3:1.0: usb_probe_interface - got id input: USB,2-axis 8-button gamepad as /devices/pci0000:00/0000:00:1d.0/usb2/2-1/2-1.2/2-1.2.3/2-1.2.3:1.0/input/input4 generic-usb 0003:0583:2060.0003: input: USB HID v1.10 Joystick [USB,2-axis 8-button gamepad ] on usb-0000:00:1d.0-1.2.3/input0 drivers/usb/core/inode.c: creating file '006' EXT4-fs (sdg6): re-mounted. Opts: (null) EXT4-fs (sdg1): mounted filesystem with ordered data mode. Opts: (null) EXT4-fs (sda7): warning: maximal mount count reached, running e2fsck is recommended EXT4-fs (sda7): mounted filesystem with ordered data mode. Opts: (null) EXT4-fs (sdb): warning: maximal mount count reached, running e2fsck is recommended EXT4-fs (sdb): recovery complete EXT4-fs (sdb): mounted filesystem with ordered data mode. Opts: (null) EXT4-fs (sdc): warning: maximal mount count reached, running e2fsck is recommended EXT4-fs (sdc): mounted filesystem with ordered data mode. Opts: (null) XFS (sde5): Mounting Filesystem XFS (sde5): Ending clean mount EXT4-fs (sdd): warning: maximal mount count reached, running e2fsck is recommended EXT4-fs (sdd): mounted filesystem with ordered data mode. Opts: (null) EXT4-fs (sdf): warning: maximal mount count reached, running e2fsck is recommended EXT4-fs (sdf): mounted filesystem with ordered data mode. Opts: (null) Adding 979928k swap on /dev/sda6. Priority:0 extents:1 across:979928k Adding 1023996k swap on /dev/sdg5. Priority:1 extents:1 across:1023996k SS ip_tables: (C) 2000-2006 Netfilter Core Team e1000e 0000:00:19.0: irq 49 for MSI/MSI-X e1000e 0000:00:19.0: irq 49 for MSI/MSI-X e1000e: eth0 NIC Link is Up 100 Mbps Full Duplex, Flow Control: Rx/Tx e1000e 0000:00:19.0: eth0: 10/100 speed: disabling TSO xhci_hcd 0000:03:00.0: Poll event ring: 4294728704 xhci_hcd 0000:03:00.0: op reg status = 0x0 xhci_hcd 0000:03:00.0: ir_set 0 pending = 0x2 xhci_hcd 0000:03:00.0: HC error bitmask = 0x4 xhci_hcd 0000:03:00.0: Event ring: xhci_hcd 0000:03:00.0: @ca807400 ca807000 00000000 01004015 0000c001 xhci_hcd 0000:03:00.0: @ca807410 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807420 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807430 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807440 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807450 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807460 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807470 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807480 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807490 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8074a0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8074b0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8074c0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8074d0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8074e0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8074f0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807500 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807510 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807520 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807530 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807540 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807550 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807560 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807570 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807580 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807590 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8075a0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8075b0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8075c0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8075d0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8075e0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8075f0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807600 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807610 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807620 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807630 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807640 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807650 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807660 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807670 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807680 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807690 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8076a0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8076b0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8076c0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8076d0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8076e0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8076f0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807700 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807710 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807720 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807730 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807740 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807750 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807760 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807770 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807780 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807790 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8077a0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8077b0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8077c0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8077d0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8077e0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8077f0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: Ring deq = ffff8800ca807410 (virt), 0xca807410 (dma) xhci_hcd 0000:03:00.0: Ring deq updated 1 times xhci_hcd 0000:03:00.0: Ring enq = ffff8800ca807400 (virt), 0xca807400 (dma) xhci_hcd 0000:03:00.0: Ring enq updated 0 times xhci_hcd 0000:03:00.0: ERST deq = 64'hca807410 xhci_hcd 0000:03:00.0: Command ring: xhci_hcd 0000:03:00.0: @ca807000 00000000 00000000 00000000 0000c401 xhci_hcd 0000:03:00.0: @ca807010 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807020 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807030 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807040 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807050 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807060 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807070 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807080 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807090 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8070a0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8070b0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8070c0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8070d0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8070e0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8070f0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807100 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807110 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807120 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807130 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807140 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807150 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807160 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807170 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807180 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807190 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8071a0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8071b0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8071c0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8071d0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8071e0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8071f0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807200 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807210 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807220 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807230 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807240 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807250 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807260 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807270 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807280 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807290 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8072a0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8072b0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8072c0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8072d0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8072e0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8072f0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807300 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807310 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807320 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807330 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807340 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807350 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807360 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807370 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807380 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca807390 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8073a0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8073b0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8073c0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8073d0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8073e0 00000000 00000000 00000000 00000000 xhci_hcd 0000:03:00.0: @ca8073f0 ca807000 00000000 00000000 00001802 xhci_hcd 0000:03:00.0: Ring deq = ffff8800ca807010 (virt), 0xca807010 (dma) xhci_hcd 0000:03:00.0: Ring deq updated 1 times xhci_hcd 0000:03:00.0: Ring enq = ffff8800ca807010 (virt), 0xca807010 (dma) xhci_hcd 0000:03:00.0: Ring enq updated 1 times xhci_hcd 0000:03:00.0: // xHC command ring deq ptr low bits + flags = @00000008 xhci_hcd 0000:03:00.0: // xHC command ring deq ptr high bits = @00000000 xhci_hcd 0000:06:00.0: Poll event ring: 4294728704 xhci_hcd 0000:06:00.0: op reg status = 0x0 xhci_hcd 0000:06:00.0: ir_set 0 pending = 0x2 xhci_hcd 0000:06:00.0: HC error bitmask = 0x4 xhci_hcd 0000:06:00.0: Event ring: xhci_hcd 0000:06:00.0: @ca80a400 ca80a000 00000000 01004015 0000c001 xhci_hcd 0000:06:00.0: @ca80a410 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a420 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a430 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a440 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a450 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a460 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a470 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a480 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a490 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a4a0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a4b0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a4c0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a4d0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a4e0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a4f0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a500 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a510 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a520 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a530 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a540 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a550 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a560 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a570 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a580 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a590 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a5a0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a5b0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a5c0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a5d0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a5e0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a5f0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a600 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a610 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a620 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a630 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a640 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a650 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a660 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a670 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a680 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a690 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a6a0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a6b0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a6c0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a6d0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a6e0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a6f0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a700 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a710 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a720 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a730 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a740 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a750 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a760 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a770 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a780 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a790 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a7a0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a7b0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a7c0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a7d0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a7e0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a7f0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: Ring deq = ffff8800ca80a410 (virt), 0xca80a410 (dma) xhci_hcd 0000:06:00.0: Ring deq updated 1 times xhci_hcd 0000:06:00.0: Ring enq = ffff8800ca80a400 (virt), 0xca80a400 (dma) xhci_hcd 0000:06:00.0: Ring enq updated 0 times xhci_hcd 0000:06:00.0: ERST deq = 64'hca80a410 xhci_hcd 0000:06:00.0: Command ring: xhci_hcd 0000:06:00.0: @ca80a000 00000000 00000000 00000000 0000c401 xhci_hcd 0000:06:00.0: @ca80a010 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a020 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a030 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a040 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a050 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a060 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a070 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a080 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a090 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a0a0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a0b0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a0c0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a0d0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a0e0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a0f0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a100 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a110 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a120 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a130 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a140 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a150 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a160 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a170 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a180 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a190 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a1a0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a1b0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a1c0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a1d0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a1e0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a1f0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a200 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a210 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a220 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a230 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a240 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a250 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a260 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a270 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a280 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a290 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a2a0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a2b0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a2c0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a2d0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a2e0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a2f0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a300 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a310 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a320 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a330 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a340 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a350 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a360 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a370 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a380 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a390 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a3a0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a3b0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a3c0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a3d0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a3e0 00000000 00000000 00000000 00000000 xhci_hcd 0000:06:00.0: @ca80a3f0 ca80a000 00000000 00000000 00001802 xhci_hcd 0000:06:00.0: Ring deq = ffff8800ca80a010 (virt), 0xca80a010 (dma) xhci_hcd 0000:06:00.0: Ring deq updated 1 times xhci_hcd 0000:06:00.0: Ring enq = ffff8800ca80a010 (virt), 0xca80a010 (dma) xhci_hcd 0000:06:00.0: Ring enq updated 1 times xhci_hcd 0000:06:00.0: // xHC command ring deq ptr low bits + flags = @00000008 xhci_hcd 0000:06:00.0: // xHC command ring deq ptr high bits = @00000000 xhci_hcd 0000:06:00.0: op reg status = 00000018 xhci_hcd 0000:06:00.0: Event ring dequeue ptr: xhci_hcd 0000:06:00.0: @ca80a410 04000000 00000000 01000000 00008801 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068024, 32'h18, 4'hf); xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: xhci_handle_event - OS owns TRB xhci_hcd 0000:06:00.0: xhci_handle_event - calling handle_port_status xhci_hcd 0000:06:00.0: Port Status Change Event for port 4 xhci_hcd 0000:06:00.0: Event ring deq = 0xca80a420 (DMA) xhci_hcd 0000:06:00.0: xhci_handle_event - returned from handle_port_status xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90000068638, 64'hca80a428, 4'hf); hub 5-0:1.0: state 7 ports 2 chg 0000 evt 0004 xhci_hcd 0000:06:00.0: get port status, actual port 1 status = 0x202e1 xhci_hcd 0000:06:00.0: Get port status returned 0x10101 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068450, 32'h202e1, 4'hf); xhci_hcd 0000:06:00.0: clear port connect change, actual port 1 status = 0x2e1 hub 5-0:1.0: port 2, status 0101, change 0001, 12 Mb/s xhci_hcd 0000:06:00.0: get port status, actual port 1 status = 0x2e1 xhci_hcd 0000:06:00.0: Get port status returned 0x101 xhci_hcd 0000:06:00.0: get port status, actual port 1 status = 0x2e1 xhci_hcd 0000:06:00.0: Get port status returned 0x101 xhci_hcd 0000:06:00.0: get port status, actual port 1 status = 0x2e1 xhci_hcd 0000:06:00.0: Get port status returned 0x101 xhci_hcd 0000:06:00.0: get port status, actual port 1 status = 0x2e1 xhci_hcd 0000:06:00.0: Get port status returned 0x101 xhci_hcd 0000:06:00.0: get port status, actual port 1 status = 0x2e1 xhci_hcd 0000:06:00.0: Get port status returned 0x101 hub 5-0:1.0: debounce: port 2: total 100ms stable 100ms status 0x101 xhci_hcd 0000:06:00.0: Endpoint state = 0x1 xhci_hcd 0000:06:00.0: Command ring enq = 0xca80a020 (DMA) xhci_hcd 0000:06:00.0: // Ding dong! xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068800, 32'h0, 4'hf); xhci_hcd 0000:06:00.0: op reg status = 00000008 xhci_hcd 0000:06:00.0: Event ring dequeue ptr: xhci_hcd 0000:06:00.0: @ca80a420 ca80a010 00000000 01000000 01008401 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068024, 32'h8, 4'hf); xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: xhci_handle_event - OS owns TRB xhci_hcd 0000:06:00.0: xhci_handle_event - calling handle_cmd_completion xhci_hcd 0000:06:00.0: Command ring deq = 0xca80a020 (DMA) xhci_hcd 0000:06:00.0: xhci_handle_event - returned from handle_cmd_completion xhci_hcd 0000:06:00.0: Event ring deq = 0xca80a430 (DMA) xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90000068638, 64'hca80a438, 4'hf); xhci_hcd 0000:06:00.0: Slot 1 output ctx = 0xca80d000 (dma) xhci_hcd 0000:06:00.0: Slot 1 input ctx = 0xca80e000 (dma) xhci_hcd 0000:06:00.0: Allocating ring at ffff88022d4ffe40 xhci_hcd 0000:06:00.0: Allocating priv segment structure at ffff88022d577d60 xhci_hcd 0000:06:00.0: // Allocating segment at ffff8800ca80a800 (virtual) 0xca80a800 (DMA) xhci_hcd 0000:06:00.0: Linking segment 0xca80a800 to segment 0xca80a800 (DMA) xhci_hcd 0000:06:00.0: Wrote link toggle flag to segment ffff88022d577d60 (virtual), 0xca80a800 (DMA) xhci_hcd 0000:06:00.0: Set slot id 1 dcbaa entry ffff8800ca809008 to 0xca80d000 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068450, 32'h2f1, 4'hf); xhci_hcd 0000:06:00.0: set port reset, actual port 1 status = 0x331 xhci_hcd 0000:06:00.0: op reg status = 00000018 xhci_hcd 0000:06:00.0: Event ring dequeue ptr: xhci_hcd 0000:06:00.0: @ca80a430 04000000 00000000 01000000 00008801 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068024, 32'h18, 4'hf); xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: xhci_handle_event - OS owns TRB xhci_hcd 0000:06:00.0: xhci_handle_event - calling handle_port_status xhci_hcd 0000:06:00.0: Port Status Change Event for port 4 xhci_hcd 0000:06:00.0: Event ring deq = 0xca80a440 (DMA) xhci_hcd 0000:06:00.0: xhci_handle_event - returned from handle_port_status xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90000068638, 64'hca80a448, 4'hf); xhci_hcd 0000:06:00.0: get port status, actual port 1 status = 0x200603 xhci_hcd 0000:06:00.0: Get port status returned 0x103 xhci_hcd 0000:06:00.0: Resetting device with slot ID 1 xhci_hcd 0000:06:00.0: Endpoint state = 0x1 xhci_hcd 0000:06:00.0: Command ring enq = 0xca80a030 (DMA) xhci_hcd 0000:06:00.0: // Ding dong! xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068800, 32'h0, 4'hf); xhci_hcd 0000:06:00.0: op reg status = 00000008 xhci_hcd 0000:06:00.0: Event ring dequeue ptr: xhci_hcd 0000:06:00.0: @ca80a440 ca80a020 00000000 13000000 01008401 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068024, 32'h8, 4'hf); xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: xhci_handle_event - OS owns TRB xhci_hcd 0000:06:00.0: xhci_handle_event - calling handle_cmd_completion xhci_hcd 0000:06:00.0: Completed reset device command. xhci_hcd 0000:06:00.0: Command ring deq = 0xca80a030 (DMA) xhci_hcd 0000:06:00.0: xhci_handle_event - returned from handle_cmd_completion xhci_hcd 0000:06:00.0: Event ring deq = 0xca80a450 (DMA) xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90000068638, 64'hca80a458, 4'hf); xhci_hcd 0000:06:00.0: Can't reset device (slot ID 1) in enabled/disabled state xhci_hcd 0000:06:00.0: Not freeing device rings. xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068450, 32'h200601, 4'hf); xhci_hcd 0000:06:00.0: clear port reset change, actual port 1 status = 0x603 usb 5-2: new full speed USB device number 2 using xhci_hcd xhci_hcd 0000:06:00.0: Set root hub portnum to 4 xhci_hcd 0000:06:00.0: Set fake root hub portnum to 2 xhci_hcd 0000:06:00.0: udev->tt = ffff88022e5cc090 xhci_hcd 0000:06:00.0: udev->ttport = 0x2 xhci_hcd 0000:06:00.0: Slot ID 1 Input Context: xhci_hcd 0000:06:00.0: @ffff8800ca80e000 (virt) @ca80e000 (dma) 0x000000 - drop flags xhci_hcd 0000:06:00.0: @ffff8800ca80e004 (virt) @ca80e004 (dma) 0x000003 - add flags xhci_hcd 0000:06:00.0: @ffff8800ca80e008 (virt) @ca80e008 (dma) 0x000000 - rsvd2[0] xhci_hcd 0000:06:00.0: @ffff8800ca80e00c (virt) @ca80e00c (dma) 0x000000 - rsvd2[1] xhci_hcd 0000:06:00.0: @ffff8800ca80e010 (virt) @ca80e010 (dma) 0x000000 - rsvd2[2] xhci_hcd 0000:06:00.0: @ffff8800ca80e014 (virt) @ca80e014 (dma) 0x000000 - rsvd2[3] xhci_hcd 0000:06:00.0: @ffff8800ca80e018 (virt) @ca80e018 (dma) 0x000000 - rsvd2[4] xhci_hcd 0000:06:00.0: @ffff8800ca80e01c (virt) @ca80e01c (dma) 0x000000 - rsvd2[5] xhci_hcd 0000:06:00.0: Slot Context: xhci_hcd 0000:06:00.0: @ffff8800ca80e020 (virt) @ca80e020 (dma) 0x8100000 - dev_info xhci_hcd 0000:06:00.0: @ffff8800ca80e024 (virt) @ca80e024 (dma) 0x040000 - dev_info2 xhci_hcd 0000:06:00.0: @ffff8800ca80e028 (virt) @ca80e028 (dma) 0x000000 - tt_info xhci_hcd 0000:06:00.0: @ffff8800ca80e02c (virt) @ca80e02c (dma) 0x000000 - dev_state xhci_hcd 0000:06:00.0: @ffff8800ca80e030 (virt) @ca80e030 (dma) 0x000000 - rsvd[0] xhci_hcd 0000:06:00.0: @ffff8800ca80e034 (virt) @ca80e034 (dma) 0x000000 - rsvd[1] xhci_hcd 0000:06:00.0: @ffff8800ca80e038 (virt) @ca80e038 (dma) 0x000000 - rsvd[2] xhci_hcd 0000:06:00.0: @ffff8800ca80e03c (virt) @ca80e03c (dma) 0x000000 - rsvd[3] xhci_hcd 0000:06:00.0: Endpoint 00 Context: xhci_hcd 0000:06:00.0: @ffff8800ca80e040 (virt) @ca80e040 (dma) 0x000000 - ep_info xhci_hcd 0000:06:00.0: @ffff8800ca80e044 (virt) @ca80e044 (dma) 0x400026 - ep_info2 xhci_hcd 0000:06:00.0: @ffff8800ca80e048 (virt) @ca80e048 (dma) 0xca80a801 - deq xhci_hcd 0000:06:00.0: @ffff8800ca80e050 (virt) @ca80e050 (dma) 0x000000 - tx_info xhci_hcd 0000:06:00.0: @ffff8800ca80e054 (virt) @ca80e054 (dma) 0x000000 - rsvd[0] xhci_hcd 0000:06:00.0: @ffff8800ca80e058 (virt) @ca80e058 (dma) 0x000000 - rsvd[1] xhci_hcd 0000:06:00.0: @ffff8800ca80e05c (virt) @ca80e05c (dma) 0x000000 - rsvd[2] xhci_hcd 0000:06:00.0: Endpoint 01 Context: xhci_hcd 0000:06:00.0: @ffff8800ca80e060 (virt) @ca80e060 (dma) 0x000000 - ep_info xhci_hcd 0000:06:00.0: @ffff8800ca80e064 (virt) @ca80e064 (dma) 0x000000 - ep_info2 xhci_hcd 0000:06:00.0: @ffff8800ca80e068 (virt) @ca80e068 (dma) 0x000000 - deq xhci_hcd 0000:06:00.0: @ffff8800ca80e070 (virt) @ca80e070 (dma) 0x000000 - tx_info xhci_hcd 0000:06:00.0: @ffff8800ca80e074 (virt) @ca80e074 (dma) 0x000000 - rsvd[0] xhci_hcd 0000:06:00.0: @ffff8800ca80e078 (virt) @ca80e078 (dma) 0x000000 - rsvd[1] xhci_hcd 0000:06:00.0: @ffff8800ca80e07c (virt) @ca80e07c (dma) 0x000000 - rsvd[2] xhci_hcd 0000:06:00.0: Endpoint 02 Context: xhci_hcd 0000:06:00.0: @ffff8800ca80e080 (virt) @ca80e080 (dma) 0x000000 - ep_info xhci_hcd 0000:06:00.0: @ffff8800ca80e084 (virt) @ca80e084 (dma) 0x000000 - ep_info2 xhci_hcd 0000:06:00.0: @ffff8800ca80e088 (virt) @ca80e088 (dma) 0x000000 - deq xhci_hcd 0000:06:00.0: @ffff8800ca80e090 (virt) @ca80e090 (dma) 0x000000 - tx_info xhci_hcd 0000:06:00.0: @ffff8800ca80e094 (virt) @ca80e094 (dma) 0x000000 - rsvd[0] xhci_hcd 0000:06:00.0: @ffff8800ca80e098 (virt) @ca80e098 (dma) 0x000000 - rsvd[1] xhci_hcd 0000:06:00.0: @ffff8800ca80e09c (virt) @ca80e09c (dma) 0x000000 - rsvd[2] xhci_hcd 0000:06:00.0: Endpoint state = 0x1 xhci_hcd 0000:06:00.0: Command ring enq = 0xca80a040 (DMA) xhci_hcd 0000:06:00.0: // Ding dong! xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068800, 32'h0, 4'hf); xhci_hcd 0000:06:00.0: op reg status = 00000008 xhci_hcd 0000:06:00.0: Event ring dequeue ptr: xhci_hcd 0000:06:00.0: @ca80a450 ca80a030 00000000 01000000 01008401 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068024, 32'h8, 4'hf); xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: xhci_handle_event - OS owns TRB xhci_hcd 0000:06:00.0: xhci_handle_event - calling handle_cmd_completion xhci_hcd 0000:06:00.0: Command ring deq = 0xca80a040 (DMA) xhci_hcd 0000:06:00.0: xhci_handle_event - returned from handle_cmd_completion xhci_hcd 0000:06:00.0: Event ring deq = 0xca80a460 (DMA) xhci_hcd 0000:06:00.0: Successful Address Device command xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: Op regs DCBAA ptr = 0x000000ca809000 xhci_hcd 0000:06:00.0: Slot ID 1 dcbaa entry @ffff8800ca809008 = 0x000000ca80d000 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90000068638, 64'hca80a468, 4'hf); xhci_hcd 0000:06:00.0: Output Context DMA address = 0xca80d000 xhci_hcd 0000:06:00.0: Slot ID 1 Input Context: xhci_hcd 0000:06:00.0: @ffff8800ca80e000 (virt) @ca80e000 (dma) 0x000000 - drop flags xhci_hcd 0000:06:00.0: @ffff8800ca80e004 (virt) @ca80e004 (dma) 0x000003 - add flags xhci_hcd 0000:06:00.0: @ffff8800ca80e008 (virt) @ca80e008 (dma) 0x000000 - rsvd2[0] xhci_hcd 0000:06:00.0: @ffff8800ca80e00c (virt) @ca80e00c (dma) 0x000000 - rsvd2[1] xhci_hcd 0000:06:00.0: @ffff8800ca80e010 (virt) @ca80e010 (dma) 0x000000 - rsvd2[2] xhci_hcd 0000:06:00.0: @ffff8800ca80e014 (virt) @ca80e014 (dma) 0x000000 - rsvd2[3] xhci_hcd 0000:06:00.0: @ffff8800ca80e018 (virt) @ca80e018 (dma) 0x000000 - rsvd2[4] xhci_hcd 0000:06:00.0: @ffff8800ca80e01c (virt) @ca80e01c (dma) 0x000000 - rsvd2[5] xhci_hcd 0000:06:00.0: Slot Context: xhci_hcd 0000:06:00.0: @ffff8800ca80e020 (virt) @ca80e020 (dma) 0x8100000 - dev_info xhci_hcd 0000:06:00.0: @ffff8800ca80e024 (virt) @ca80e024 (dma) 0x040000 - dev_info2 xhci_hcd 0000:06:00.0: @ffff8800ca80e028 (virt) @ca80e028 (dma) 0x000000 - tt_info xhci_hcd 0000:06:00.0: @ffff8800ca80e02c (virt) @ca80e02c (dma) 0x000000 - dev_state xhci_hcd 0000:06:00.0: @ffff8800ca80e030 (virt) @ca80e030 (dma) 0x000000 - rsvd[0] xhci_hcd 0000:06:00.0: @ffff8800ca80e034 (virt) @ca80e034 (dma) 0x000000 - rsvd[1] xhci_hcd 0000:06:00.0: @ffff8800ca80e038 (virt) @ca80e038 (dma) 0x000000 - rsvd[2] xhci_hcd 0000:06:00.0: @ffff8800ca80e03c (virt) @ca80e03c (dma) 0x000000 - rsvd[3] xhci_hcd 0000:06:00.0: Endpoint 00 Context: xhci_hcd 0000:06:00.0: @ffff8800ca80e040 (virt) @ca80e040 (dma) 0x000000 - ep_info xhci_hcd 0000:06:00.0: @ffff8800ca80e044 (virt) @ca80e044 (dma) 0x400026 - ep_info2 xhci_hcd 0000:06:00.0: @ffff8800ca80e048 (virt) @ca80e048 (dma) 0xca80a801 - deq xhci_hcd 0000:06:00.0: @ffff8800ca80e050 (virt) @ca80e050 (dma) 0x000000 - tx_info xhci_hcd 0000:06:00.0: @ffff8800ca80e054 (virt) @ca80e054 (dma) 0x000000 - rsvd[0] xhci_hcd 0000:06:00.0: @ffff8800ca80e058 (virt) @ca80e058 (dma) 0x000000 - rsvd[1] xhci_hcd 0000:06:00.0: @ffff8800ca80e05c (virt) @ca80e05c (dma) 0x000000 - rsvd[2] xhci_hcd 0000:06:00.0: Endpoint 01 Context: xhci_hcd 0000:06:00.0: @ffff8800ca80e060 (virt) @ca80e060 (dma) 0x000000 - ep_info xhci_hcd 0000:06:00.0: @ffff8800ca80e064 (virt) @ca80e064 (dma) 0x000000 - ep_info2 xhci_hcd 0000:06:00.0: @ffff8800ca80e068 (virt) @ca80e068 (dma) 0x000000 - deq xhci_hcd 0000:06:00.0: @ffff8800ca80e070 (virt) @ca80e070 (dma) 0x000000 - tx_info xhci_hcd 0000:06:00.0: @ffff8800ca80e074 (virt) @ca80e074 (dma) 0x000000 - rsvd[0] xhci_hcd 0000:06:00.0: @ffff8800ca80e078 (virt) @ca80e078 (dma) 0x000000 - rsvd[1] xhci_hcd 0000:06:00.0: @ffff8800ca80e07c (virt) @ca80e07c (dma) 0x000000 - rsvd[2] xhci_hcd 0000:06:00.0: Endpoint 02 Context: xhci_hcd 0000:06:00.0: @ffff8800ca80e080 (virt) @ca80e080 (dma) 0x000000 - ep_info xhci_hcd 0000:06:00.0: @ffff8800ca80e084 (virt) @ca80e084 (dma) 0x000000 - ep_info2 xhci_hcd 0000:06:00.0: @ffff8800ca80e088 (virt) @ca80e088 (dma) 0x000000 - deq xhci_hcd 0000:06:00.0: @ffff8800ca80e090 (virt) @ca80e090 (dma) 0x000000 - tx_info xhci_hcd 0000:06:00.0: @ffff8800ca80e094 (virt) @ca80e094 (dma) 0x000000 - rsvd[0] xhci_hcd 0000:06:00.0: @ffff8800ca80e098 (virt) @ca80e098 (dma) 0x000000 - rsvd[1] xhci_hcd 0000:06:00.0: @ffff8800ca80e09c (virt) @ca80e09c (dma) 0x000000 - rsvd[2] xhci_hcd 0000:06:00.0: Slot ID 1 Output Context: xhci_hcd 0000:06:00.0: Slot Context: xhci_hcd 0000:06:00.0: @ffff8800ca80d000 (virt) @ca80d000 (dma) 0x8100000 - dev_info xhci_hcd 0000:06:00.0: @ffff8800ca80d004 (virt) @ca80d004 (dma) 0x040000 - dev_info2 xhci_hcd 0000:06:00.0: @ffff8800ca80d008 (virt) @ca80d008 (dma) 0x000000 - tt_info xhci_hcd 0000:06:00.0: @ffff8800ca80d00c (virt) @ca80d00c (dma) 0x10000001 - dev_state xhci_hcd 0000:06:00.0: @ffff8800ca80d010 (virt) @ca80d010 (dma) 0x000000 - rsvd[0] xhci_hcd 0000:06:00.0: @ffff8800ca80d014 (virt) @ca80d014 (dma) 0x000000 - rsvd[1] xhci_hcd 0000:06:00.0: @ffff8800ca80d018 (virt) @ca80d018 (dma) 0x000000 - rsvd[2] xhci_hcd 0000:06:00.0: @ffff8800ca80d01c (virt) @ca80d01c (dma) 0x000000 - rsvd[3] xhci_hcd 0000:06:00.0: Endpoint 00 Context: xhci_hcd 0000:06:00.0: @ffff8800ca80d020 (virt) @ca80d020 (dma) 0x000001 - ep_info xhci_hcd 0000:06:00.0: @ffff8800ca80d024 (virt) @ca80d024 (dma) 0x400026 - ep_info2 xhci_hcd 0000:06:00.0: @ffff8800ca80d028 (virt) @ca80d028 (dma) 0xca80a801 - deq xhci_hcd 0000:06:00.0: @ffff8800ca80d030 (virt) @ca80d030 (dma) 0x000000 - tx_info xhci_hcd 0000:06:00.0: @ffff8800ca80d034 (virt) @ca80d034 (dma) 0x000000 - rsvd[0] xhci_hcd 0000:06:00.0: @ffff8800ca80d038 (virt) @ca80d038 (dma) 0x000000 - rsvd[1] xhci_hcd 0000:06:00.0: @ffff8800ca80d03c (virt) @ca80d03c (dma) 0x000000 - rsvd[2] xhci_hcd 0000:06:00.0: Endpoint 01 Context: xhci_hcd 0000:06:00.0: @ffff8800ca80d040 (virt) @ca80d040 (dma) 0x000000 - ep_info xhci_hcd 0000:06:00.0: @ffff8800ca80d044 (virt) @ca80d044 (dma) 0x000000 - ep_info2 xhci_hcd 0000:06:00.0: @ffff8800ca80d048 (virt) @ca80d048 (dma) 0x000000 - deq xhci_hcd 0000:06:00.0: @ffff8800ca80d050 (virt) @ca80d050 (dma) 0x000000 - tx_info xhci_hcd 0000:06:00.0: @ffff8800ca80d054 (virt) @ca80d054 (dma) 0x000000 - rsvd[0] xhci_hcd 0000:06:00.0: @ffff8800ca80d058 (virt) @ca80d058 (dma) 0x000000 - rsvd[1] xhci_hcd 0000:06:00.0: @ffff8800ca80d05c (virt) @ca80d05c (dma) 0x000000 - rsvd[2] xhci_hcd 0000:06:00.0: Endpoint 02 Context: xhci_hcd 0000:06:00.0: @ffff8800ca80d060 (virt) @ca80d060 (dma) 0x000000 - ep_info xhci_hcd 0000:06:00.0: @ffff8800ca80d064 (virt) @ca80d064 (dma) 0x000000 - ep_info2 xhci_hcd 0000:06:00.0: @ffff8800ca80d068 (virt) @ca80d068 (dma) 0x000000 - deq xhci_hcd 0000:06:00.0: @ffff8800ca80d070 (virt) @ca80d070 (dma) 0x000000 - tx_info xhci_hcd 0000:06:00.0: @ffff8800ca80d074 (virt) @ca80d074 (dma) 0x000000 - rsvd[0] xhci_hcd 0000:06:00.0: @ffff8800ca80d078 (virt) @ca80d078 (dma) 0x000000 - rsvd[1] xhci_hcd 0000:06:00.0: @ffff8800ca80d07c (virt) @ca80d07c (dma) 0x000000 - rsvd[2] xhci_hcd 0000:06:00.0: Internal device address = 2 xhci_hcd 0000:06:00.0: Queueing ctrl tx for slot id 1, ep 0 xhci_hcd 0000:06:00.0: Endpoint state = 0x1 xhci_hcd 0000:06:00.0: Ring enq = 0xca80a810 (DMA) xhci_hcd 0000:06:00.0: Ring enq = 0xca80a820 (DMA) xhci_hcd 0000:06:00.0: Ring enq = 0xca80a830 (DMA) xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068804, 32'h1, 4'hf); xhci_hcd 0000:06:00.0: op reg status = 00000008 xhci_hcd 0000:06:00.0: Event ring dequeue ptr: xhci_hcd 0000:06:00.0: @ca80a460 ca80a820 00000000 01000000 01018001 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068024, 32'h8, 4'hf); xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: xhci_handle_event - OS owns TRB xhci_hcd 0000:06:00.0: xhci_handle_event - calling handle_tx_event xhci_hcd 0000:06:00.0: handle_tx_event - ep index = 0 xhci_hcd 0000:06:00.0: DMA address or buffer contents= 3397429280 xhci_hcd 0000:06:00.0: Successful control transfer! xhci_hcd 0000:06:00.0: Ring deq = 0xca80a810 (DMA) xhci_hcd 0000:06:00.0: Ring deq = 0xca80a820 (DMA) xhci_hcd 0000:06:00.0: Ring deq = 0xca80a830 (DMA) xhci_hcd 0000:06:00.0: Event ring deq = 0xca80a470 (DMA) xhci_hcd 0000:06:00.0: Giveback URB ffff8801f5bdd600, len = 8, status = 0 xhci_hcd 0000:06:00.0: xhci_handle_event - returned from handle_tx_event xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90000068638, 64'hca80a478, 4'hf); usb 5-2: ep0 maxpacket = 32 xhci_hcd 0000:06:00.0: Max Packet Size for ep 0 changed. xhci_hcd 0000:06:00.0: Max packet size in usb_device = 32 xhci_hcd 0000:06:00.0: Max packet size in xHCI HW = 64 xhci_hcd 0000:06:00.0: Issuing evaluate context command. xhci_hcd 0000:06:00.0: Slot 1 input context xhci_hcd 0000:06:00.0: @ffff8800ca80e000 (virt) @ca80e000 (dma) 0x000000 - drop flags xhci_hcd 0000:06:00.0: @ffff8800ca80e004 (virt) @ca80e004 (dma) 0x000002 - add flags xhci_hcd 0000:06:00.0: @ffff8800ca80e008 (virt) @ca80e008 (dma) 0x000000 - rsvd2[0] xhci_hcd 0000:06:00.0: @ffff8800ca80e00c (virt) @ca80e00c (dma) 0x000000 - rsvd2[1] xhci_hcd 0000:06:00.0: @ffff8800ca80e010 (virt) @ca80e010 (dma) 0x000000 - rsvd2[2] xhci_hcd 0000:06:00.0: @ffff8800ca80e014 (virt) @ca80e014 (dma) 0x000000 - rsvd2[3] xhci_hcd 0000:06:00.0: @ffff8800ca80e018 (virt) @ca80e018 (dma) 0x000000 - rsvd2[4] xhci_hcd 0000:06:00.0: @ffff8800ca80e01c (virt) @ca80e01c (dma) 0x000000 - rsvd2[5] xhci_hcd 0000:06:00.0: Slot Context: xhci_hcd 0000:06:00.0: @ffff8800ca80e020 (virt) @ca80e020 (dma) 0x8100000 - dev_info xhci_hcd 0000:06:00.0: @ffff8800ca80e024 (virt) @ca80e024 (dma) 0x040000 - dev_info2 xhci_hcd 0000:06:00.0: @ffff8800ca80e028 (virt) @ca80e028 (dma) 0x000000 - tt_info xhci_hcd 0000:06:00.0: @ffff8800ca80e02c (virt) @ca80e02c (dma) 0x000000 - dev_state xhci_hcd 0000:06:00.0: @ffff8800ca80e030 (virt) @ca80e030 (dma) 0x000000 - rsvd[0] xhci_hcd 0000:06:00.0: @ffff8800ca80e034 (virt) @ca80e034 (dma) 0x000000 - rsvd[1] xhci_hcd 0000:06:00.0: @ffff8800ca80e038 (virt) @ca80e038 (dma) 0x000000 - rsvd[2] xhci_hcd 0000:06:00.0: @ffff8800ca80e03c (virt) @ca80e03c (dma) 0x000000 - rsvd[3] xhci_hcd 0000:06:00.0: Endpoint 00 Context: xhci_hcd 0000:06:00.0: @ffff8800ca80e040 (virt) @ca80e040 (dma) 0x000001 - ep_info xhci_hcd 0000:06:00.0: @ffff8800ca80e044 (virt) @ca80e044 (dma) 0x200026 - ep_info2 xhci_hcd 0000:06:00.0: @ffff8800ca80e048 (virt) @ca80e048 (dma) 0xca80a801 - deq xhci_hcd 0000:06:00.0: @ffff8800ca80e050 (virt) @ca80e050 (dma) 0x000000 - tx_info xhci_hcd 0000:06:00.0: @ffff8800ca80e054 (virt) @ca80e054 (dma) 0x000000 - rsvd[0] xhci_hcd 0000:06:00.0: @ffff8800ca80e058 (virt) @ca80e058 (dma) 0x000000 - rsvd[1] xhci_hcd 0000:06:00.0: @ffff8800ca80e05c (virt) @ca80e05c (dma) 0x000000 - rsvd[2] xhci_hcd 0000:06:00.0: Slot 1 output context xhci_hcd 0000:06:00.0: Slot Context: xhci_hcd 0000:06:00.0: @ffff8800ca80d000 (virt) @ca80d000 (dma) 0x8100000 - dev_info xhci_hcd 0000:06:00.0: @ffff8800ca80d004 (virt) @ca80d004 (dma) 0x040000 - dev_info2 xhci_hcd 0000:06:00.0: @ffff8800ca80d008 (virt) @ca80d008 (dma) 0x000000 - tt_info xhci_hcd 0000:06:00.0: @ffff8800ca80d00c (virt) @ca80d00c (dma) 0x10000001 - dev_state xhci_hcd 0000:06:00.0: @ffff8800ca80d010 (virt) @ca80d010 (dma) 0x000000 - rsvd[0] xhci_hcd 0000:06:00.0: @ffff8800ca80d014 (virt) @ca80d014 (dma) 0x000000 - rsvd[1] xhci_hcd 0000:06:00.0: @ffff8800ca80d018 (virt) @ca80d018 (dma) 0x000000 - rsvd[2] xhci_hcd 0000:06:00.0: @ffff8800ca80d01c (virt) @ca80d01c (dma) 0x000000 - rsvd[3] xhci_hcd 0000:06:00.0: Endpoint 00 Context: xhci_hcd 0000:06:00.0: @ffff8800ca80d020 (virt) @ca80d020 (dma) 0x000001 - ep_info xhci_hcd 0000:06:00.0: @ffff8800ca80d024 (virt) @ca80d024 (dma) 0x400026 - ep_info2 xhci_hcd 0000:06:00.0: @ffff8800ca80d028 (virt) @ca80d028 (dma) 0xca80a801 - deq xhci_hcd 0000:06:00.0: @ffff8800ca80d030 (virt) @ca80d030 (dma) 0x000000 - tx_info xhci_hcd 0000:06:00.0: @ffff8800ca80d034 (virt) @ca80d034 (dma) 0x000000 - rsvd[0] xhci_hcd 0000:06:00.0: @ffff8800ca80d038 (virt) @ca80d038 (dma) 0x000000 - rsvd[1] xhci_hcd 0000:06:00.0: @ffff8800ca80d03c (virt) @ca80d03c (dma) 0x000000 - rsvd[2] xhci_hcd 0000:06:00.0: Endpoint state = 0x1 xhci_hcd 0000:06:00.0: Command ring enq = 0xca80a050 (DMA) xhci_hcd 0000:06:00.0: // Ding dong! xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068800, 32'h0, 4'hf); xhci_hcd 0000:06:00.0: op reg status = 00000008 xhci_hcd 0000:06:00.0: Event ring dequeue ptr: xhci_hcd 0000:06:00.0: @ca80a470 ca80a040 00000000 01000000 01008401 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068024, 32'h8, 4'hf); xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: xhci_handle_event - OS owns TRB xhci_hcd 0000:06:00.0: xhci_handle_event - calling handle_cmd_completion xhci_hcd 0000:06:00.0: Command ring deq = 0xca80a050 (DMA) xhci_hcd 0000:06:00.0: xhci_handle_event - returned from handle_cmd_completion xhci_hcd 0000:06:00.0: Event ring deq = 0xca80a480 (DMA) xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90000068638, 64'hca80a488, 4'hf); usb 5-2: Successful evaluate context command xhci_hcd 0000:06:00.0: Queueing ctrl tx for slot id 1, ep 0 xhci_hcd 0000:06:00.0: Endpoint state = 0x1 xhci_hcd 0000:06:00.0: Ring enq = 0xca80a840 (DMA) xhci_hcd 0000:06:00.0: Ring enq = 0xca80a850 (DMA) xhci_hcd 0000:06:00.0: Ring enq = 0xca80a860 (DMA) xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068804, 32'h1, 4'hf); xhci_hcd 0000:06:00.0: op reg status = 00000008 xhci_hcd 0000:06:00.0: Event ring dequeue ptr: xhci_hcd 0000:06:00.0: @ca80a480 ca80a850 00000000 01000000 01018001 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068024, 32'h8, 4'hf); xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: xhci_handle_event - OS owns TRB xhci_hcd 0000:06:00.0: xhci_handle_event - calling handle_tx_event xhci_hcd 0000:06:00.0: handle_tx_event - ep index = 0 xhci_hcd 0000:06:00.0: DMA address or buffer contents= 3397429328 xhci_hcd 0000:06:00.0: Successful control transfer! xhci_hcd 0000:06:00.0: Ring deq = 0xca80a840 (DMA) xhci_hcd 0000:06:00.0: Ring deq = 0xca80a850 (DMA) xhci_hcd 0000:06:00.0: Ring deq = 0xca80a860 (DMA) xhci_hcd 0000:06:00.0: Event ring deq = 0xca80a490 (DMA) xhci_hcd 0000:06:00.0: Giveback URB ffff8801f5624240, len = 18, status = 0 xhci_hcd 0000:06:00.0: xhci_handle_event - returned from handle_tx_event xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90000068638, 64'hca80a498, 4'hf); xhci_hcd 0000:06:00.0: Queueing ctrl tx for slot id 1, ep 0 xhci_hcd 0000:06:00.0: Endpoint state = 0x1 xhci_hcd 0000:06:00.0: Ring enq = 0xca80a870 (DMA) xhci_hcd 0000:06:00.0: Ring enq = 0xca80a880 (DMA) xhci_hcd 0000:06:00.0: Ring enq = 0xca80a890 (DMA) xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068804, 32'h1, 4'hf); xhci_hcd 0000:06:00.0: op reg status = 00000008 xhci_hcd 0000:06:00.0: Event ring dequeue ptr: xhci_hcd 0000:06:00.0: @ca80a490 ca80a870 00000000 0600000a 01018001 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068024, 32'h8, 4'hf); xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: xhci_handle_event - OS owns TRB xhci_hcd 0000:06:00.0: xhci_handle_event - calling handle_tx_event xhci_hcd 0000:06:00.0: handle_tx_event - ep index = 0 xhci_hcd 0000:06:00.0: WARN: Stalled endpoint xhci_hcd 0000:06:00.0: DMA address or buffer contents= 3397429360 xhci_hcd 0000:06:00.0: Endpoint state = 0x1 xhci_hcd 0000:06:00.0: Command ring enq = 0xca80a060 (DMA) xhci_hcd 0000:06:00.0: Cleaning up stalled endpoint ring xhci_hcd 0000:06:00.0: Finding segment containing stopped TRB. xhci_hcd 0000:06:00.0: Finding endpoint context xhci_hcd 0000:06:00.0: Finding segment containing last TRB in TD. xhci_hcd 0000:06:00.0: Cycle state = 0x1 xhci_hcd 0000:06:00.0: New dequeue segment = ffff88022d577d60 (virtual) xhci_hcd 0000:06:00.0: New dequeue pointer = 0xca80a890 (DMA) xhci_hcd 0000:06:00.0: Queueing new dequeue state xhci_hcd 0000:06:00.0: Set TR Deq Ptr cmd, new deq seg = ffff88022d577d60 (0xca80a800 dma), new deq ptr = ffff8800ca80a890 (0xca80a890 dma), new cycle = 1 xhci_hcd 0000:06:00.0: Endpoint state = 0x1 xhci_hcd 0000:06:00.0: Command ring enq = 0xca80a070 (DMA) xhci_hcd 0000:06:00.0: // Ding dong! xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068800, 32'h0, 4'hf); xhci_hcd 0000:06:00.0: Event ring deq = 0xca80a4a0 (DMA) xhci_hcd 0000:06:00.0: Giveback URB ffff8801f5bdd6c0, len = 0, status = -32 xhci_hcd 0000:06:00.0: xhci_handle_event - returned from handle_tx_event xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90000068638, 64'hca80a4a8, 4'hf); xhci_hcd 0000:06:00.0: Queueing ctrl tx for slot id 1, ep 0 xhci_hcd 0000:06:00.0: Endpoint state = 0x2 xhci_hcd 0000:06:00.0: WARN halted endpoint, queueing URB anyway. xhci_hcd 0000:06:00.0: Ring enq = 0xca80a8a0 (DMA) xhci_hcd 0000:06:00.0: Ring enq = 0xca80a8b0 (DMA) xhci_hcd 0000:06:00.0: Ring enq = 0xca80a8c0 (DMA) xhci_hcd 0000:06:00.0: op reg status = 00000008 xhci_hcd 0000:06:00.0: Event ring dequeue ptr: xhci_hcd 0000:06:00.0: @ca80a4a0 ca80a050 00000000 01000000 01008401 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068024, 32'h8, 4'hf); xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: xhci_handle_event - OS owns TRB xhci_hcd 0000:06:00.0: xhci_handle_event - calling handle_cmd_completion xhci_hcd 0000:06:00.0: Ignoring reset ep completion code of 1 xhci_hcd 0000:06:00.0: Command ring deq = 0xca80a060 (DMA) xhci_hcd 0000:06:00.0: xhci_handle_event - returned from handle_cmd_completion xhci_hcd 0000:06:00.0: Event ring deq = 0xca80a4b0 (DMA) xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90000068638, 64'hca80a4b8, 4'hf); xhci_hcd 0000:06:00.0: op reg status = 00000008 xhci_hcd 0000:06:00.0: Event ring dequeue ptr: xhci_hcd 0000:06:00.0: @ca80a4b0 ca80a060 00000000 01000000 01008401 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068024, 32'h8, 4'hf); xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: xhci_handle_event - OS owns TRB xhci_hcd 0000:06:00.0: xhci_handle_event - calling handle_cmd_completion xhci_hcd 0000:06:00.0: Successful Set TR Deq Ptr cmd, deq = @ca80a891 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068804, 32'h1, 4'hf); xhci_hcd 0000:06:00.0: Command ring deq = 0xca80a070 (DMA) xhci_hcd 0000:06:00.0: xhci_handle_event - returned from handle_cmd_completion xhci_hcd 0000:06:00.0: Event ring deq = 0xca80a4c0 (DMA) xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90000068638, 64'hca80a4c8, 4'hf); xhci_hcd 0000:06:00.0: op reg status = 00000008 xhci_hcd 0000:06:00.0: Event ring dequeue ptr: xhci_hcd 0000:06:00.0: @ca80a4c0 ca80a8a0 00000000 0600000a 01018001 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068024, 32'h8, 4'hf); xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: xhci_handle_event - OS owns TRB xhci_hcd 0000:06:00.0: xhci_handle_event - calling handle_tx_event xhci_hcd 0000:06:00.0: handle_tx_event - ep index = 0 xhci_hcd 0000:06:00.0: WARN: Stalled endpoint xhci_hcd 0000:06:00.0: DMA address or buffer contents= 3397429408 xhci_hcd 0000:06:00.0: Endpoint state = 0x1 xhci_hcd 0000:06:00.0: Command ring enq = 0xca80a080 (DMA) xhci_hcd 0000:06:00.0: Cleaning up stalled endpoint ring xhci_hcd 0000:06:00.0: Finding segment containing stopped TRB. xhci_hcd 0000:06:00.0: Finding endpoint context xhci_hcd 0000:06:00.0: Finding segment containing last TRB in TD. xhci_hcd 0000:06:00.0: Cycle state = 0x1 xhci_hcd 0000:06:00.0: New dequeue segment = ffff88022d577d60 (virtual) xhci_hcd 0000:06:00.0: New dequeue pointer = 0xca80a8c0 (DMA) xhci_hcd 0000:06:00.0: Queueing new dequeue state xhci_hcd 0000:06:00.0: Set TR Deq Ptr cmd, new deq seg = ffff88022d577d60 (0xca80a800 dma), new deq ptr = ffff8800ca80a8c0 (0xca80a8c0 dma), new cycle = 1 xhci_hcd 0000:06:00.0: Endpoint state = 0x1 xhci_hcd 0000:06:00.0: Command ring enq = 0xca80a090 (DMA) xhci_hcd 0000:06:00.0: // Ding dong! xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068800, 32'h0, 4'hf); xhci_hcd 0000:06:00.0: Event ring deq = 0xca80a4d0 (DMA) xhci_hcd 0000:06:00.0: Giveback URB ffff8801f5624300, len = 0, status = -32 xhci_hcd 0000:06:00.0: xhci_handle_event - returned from handle_tx_event xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90000068638, 64'hca80a4d8, 4'hf); xhci_hcd 0000:06:00.0: Queueing ctrl tx for slot id 1, ep 0 xhci_hcd 0000:06:00.0: Endpoint state = 0x2 xhci_hcd 0000:06:00.0: WARN halted endpoint, queueing URB anyway. xhci_hcd 0000:06:00.0: Ring enq = 0xca80a8d0 (DMA) xhci_hcd 0000:06:00.0: Ring enq = 0xca80a8e0 (DMA) xhci_hcd 0000:06:00.0: Ring enq = 0xca80a8f0 (DMA) xhci_hcd 0000:06:00.0: op reg status = 00000008 xhci_hcd 0000:06:00.0: Event ring dequeue ptr: xhci_hcd 0000:06:00.0: @ca80a4d0 ca80a070 00000000 01000000 01008401 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068024, 32'h8, 4'hf); xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: xhci_handle_event - OS owns TRB xhci_hcd 0000:06:00.0: xhci_handle_event - calling handle_cmd_completion xhci_hcd 0000:06:00.0: Ignoring reset ep completion code of 1 xhci_hcd 0000:06:00.0: Command ring deq = 0xca80a080 (DMA) xhci_hcd 0000:06:00.0: xhci_handle_event - returned from handle_cmd_completion xhci_hcd 0000:06:00.0: Event ring deq = 0xca80a4e0 (DMA) xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90000068638, 64'hca80a4e8, 4'hf); xhci_hcd 0000:06:00.0: op reg status = 00000008 xhci_hcd 0000:06:00.0: Event ring dequeue ptr: xhci_hcd 0000:06:00.0: @ca80a4e0 ca80a080 00000000 01000000 01008401 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068024, 32'h8, 4'hf); xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: xhci_handle_event - OS owns TRB xhci_hcd 0000:06:00.0: xhci_handle_event - calling handle_cmd_completion xhci_hcd 0000:06:00.0: Successful Set TR Deq Ptr cmd, deq = @ca80a8c1 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068804, 32'h1, 4'hf); xhci_hcd 0000:06:00.0: Command ring deq = 0xca80a090 (DMA) xhci_hcd 0000:06:00.0: xhci_handle_event - returned from handle_cmd_completion xhci_hcd 0000:06:00.0: Event ring deq = 0xca80a4f0 (DMA) xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90000068638, 64'hca80a4f8, 4'hf); xhci_hcd 0000:06:00.0: op reg status = 00000008 xhci_hcd 0000:06:00.0: Event ring dequeue ptr: xhci_hcd 0000:06:00.0: @ca80a4f0 ca80a8d0 00000000 0600000a 01018001 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068024, 32'h8, 4'hf); xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: xhci_handle_event - OS owns TRB xhci_hcd 0000:06:00.0: xhci_handle_event - calling handle_tx_event xhci_hcd 0000:06:00.0: handle_tx_event - ep index = 0 xhci_hcd 0000:06:00.0: WARN: Stalled endpoint xhci_hcd 0000:06:00.0: DMA address or buffer contents= 3397429456 xhci_hcd 0000:06:00.0: Endpoint state = 0x1 xhci_hcd 0000:06:00.0: Command ring enq = 0xca80a0a0 (DMA) xhci_hcd 0000:06:00.0: Cleaning up stalled endpoint ring xhci_hcd 0000:06:00.0: Finding segment containing stopped TRB. xhci_hcd 0000:06:00.0: Finding endpoint context xhci_hcd 0000:06:00.0: Finding segment containing last TRB in TD. xhci_hcd 0000:06:00.0: Cycle state = 0x1 xhci_hcd 0000:06:00.0: New dequeue segment = ffff88022d577d60 (virtual) xhci_hcd 0000:06:00.0: New dequeue pointer = 0xca80a8f0 (DMA) xhci_hcd 0000:06:00.0: Queueing new dequeue state xhci_hcd 0000:06:00.0: Set TR Deq Ptr cmd, new deq seg = ffff88022d577d60 (0xca80a800 dma), new deq ptr = ffff8800ca80a8f0 (0xca80a8f0 dma), new cycle = 1 xhci_hcd 0000:06:00.0: Endpoint state = 0x1 xhci_hcd 0000:06:00.0: Command ring enq = 0xca80a0b0 (DMA) xhci_hcd 0000:06:00.0: // Ding dong! xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068800, 32'h0, 4'hf); xhci_hcd 0000:06:00.0: Event ring deq = 0xca80a500 (DMA) xhci_hcd 0000:06:00.0: Giveback URB ffff8801f5bdd300, len = 0, status = -32 xhci_hcd 0000:06:00.0: xhci_handle_event - returned from handle_tx_event xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90000068638, 64'hca80a508, 4'hf); xhci_hcd 0000:06:00.0: Queueing ctrl tx for slot id 1, ep 0 xhci_hcd 0000:06:00.0: Endpoint state = 0x2 xhci_hcd 0000:06:00.0: WARN halted endpoint, queueing URB anyway. xhci_hcd 0000:06:00.0: Ring enq = 0xca80a900 (DMA) xhci_hcd 0000:06:00.0: Ring enq = 0xca80a910 (DMA) xhci_hcd 0000:06:00.0: Ring enq = 0xca80a920 (DMA) xhci_hcd 0000:06:00.0: op reg status = 00000008 xhci_hcd 0000:06:00.0: Event ring dequeue ptr: xhci_hcd 0000:06:00.0: @ca80a500 ca80a090 00000000 01000000 01008401 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068024, 32'h8, 4'hf); xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: xhci_handle_event - OS owns TRB xhci_hcd 0000:06:00.0: xhci_handle_event - calling handle_cmd_completion xhci_hcd 0000:06:00.0: Ignoring reset ep completion code of 1 xhci_hcd 0000:06:00.0: Command ring deq = 0xca80a0a0 (DMA) xhci_hcd 0000:06:00.0: xhci_handle_event - returned from handle_cmd_completion xhci_hcd 0000:06:00.0: Event ring deq = 0xca80a510 (DMA) xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90000068638, 64'hca80a518, 4'hf); xhci_hcd 0000:06:00.0: op reg status = 00000008 xhci_hcd 0000:06:00.0: Event ring dequeue ptr: xhci_hcd 0000:06:00.0: @ca80a510 ca80a0a0 00000000 01000000 01008401 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068024, 32'h8, 4'hf); xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: xhci_handle_event - OS owns TRB xhci_hcd 0000:06:00.0: xhci_handle_event - calling handle_cmd_completion xhci_hcd 0000:06:00.0: Successful Set TR Deq Ptr cmd, deq = @ca80a8f1 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068804, 32'h1, 4'hf); xhci_hcd 0000:06:00.0: Command ring deq = 0xca80a0b0 (DMA) xhci_hcd 0000:06:00.0: xhci_handle_event - returned from handle_cmd_completion xhci_hcd 0000:06:00.0: Event ring deq = 0xca80a520 (DMA) xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90000068638, 64'hca80a528, 4'hf); xhci_hcd 0000:06:00.0: op reg status = 00000008 xhci_hcd 0000:06:00.0: Event ring dequeue ptr: xhci_hcd 0000:06:00.0: @ca80a520 ca80a910 00000000 01000000 01018001 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068024, 32'h8, 4'hf); xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: xhci_handle_event - OS owns TRB xhci_hcd 0000:06:00.0: xhci_handle_event - calling handle_tx_event xhci_hcd 0000:06:00.0: handle_tx_event - ep index = 0 xhci_hcd 0000:06:00.0: DMA address or buffer contents= 3397429520 xhci_hcd 0000:06:00.0: Successful control transfer! xhci_hcd 0000:06:00.0: Ring deq = 0xca80a900 (DMA) xhci_hcd 0000:06:00.0: Ring deq = 0xca80a910 (DMA) xhci_hcd 0000:06:00.0: Ring deq = 0xca80a920 (DMA) xhci_hcd 0000:06:00.0: Event ring deq = 0xca80a530 (DMA) xhci_hcd 0000:06:00.0: Giveback URB ffff8801f5bdd300, len = 9, status = 0 xhci_hcd 0000:06:00.0: xhci_handle_event - returned from handle_tx_event xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90000068638, 64'hca80a538, 4'hf); xhci_hcd 0000:06:00.0: Queueing ctrl tx for slot id 1, ep 0 xhci_hcd 0000:06:00.0: Endpoint state = 0x1 xhci_hcd 0000:06:00.0: Ring enq = 0xca80a930 (DMA) xhci_hcd 0000:06:00.0: Ring enq = 0xca80a940 (DMA) xhci_hcd 0000:06:00.0: Ring enq = 0xca80a950 (DMA) xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068804, 32'h1, 4'hf); xhci_hcd 0000:06:00.0: op reg status = 00000008 xhci_hcd 0000:06:00.0: Event ring dequeue ptr: xhci_hcd 0000:06:00.0: @ca80a530 ca80a940 00000000 01000000 01018001 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068024, 32'h8, 4'hf); xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: xhci_handle_event - OS owns TRB xhci_hcd 0000:06:00.0: xhci_handle_event - calling handle_tx_event xhci_hcd 0000:06:00.0: handle_tx_event - ep index = 0 xhci_hcd 0000:06:00.0: DMA address or buffer contents= 3397429568 xhci_hcd 0000:06:00.0: Successful control transfer! xhci_hcd 0000:06:00.0: Ring deq = 0xca80a930 (DMA) xhci_hcd 0000:06:00.0: Ring deq = 0xca80a940 (DMA) xhci_hcd 0000:06:00.0: Ring deq = 0xca80a950 (DMA) xhci_hcd 0000:06:00.0: Event ring deq = 0xca80a540 (DMA) xhci_hcd 0000:06:00.0: Giveback URB ffff8801f56243c0, len = 59, status = 0 xhci_hcd 0000:06:00.0: xhci_handle_event - returned from handle_tx_event xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90000068638, 64'hca80a548, 4'hf); usb 5-2: skipped 1 descriptor after interface usb 5-2: skipped 1 descriptor after interface xhci_hcd 0000:06:00.0: Queueing ctrl tx for slot id 1, ep 0 xhci_hcd 0000:06:00.0: Endpoint state = 0x1 xhci_hcd 0000:06:00.0: Ring enq = 0xca80a960 (DMA) xhci_hcd 0000:06:00.0: Ring enq = 0xca80a970 (DMA) xhci_hcd 0000:06:00.0: Ring enq = 0xca80a980 (DMA) xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068804, 32'h1, 4'hf); xhci_hcd 0000:06:00.0: op reg status = 00000008 xhci_hcd 0000:06:00.0: Event ring dequeue ptr: xhci_hcd 0000:06:00.0: @ca80a540 ca80a960 00000000 0d0000fb 01018001 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068024, 32'h8, 4'hf); xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: xhci_handle_event - OS owns TRB xhci_hcd 0000:06:00.0: xhci_handle_event - calling handle_tx_event xhci_hcd 0000:06:00.0: handle_tx_event - ep index = 0 xhci_hcd 0000:06:00.0: DMA address or buffer contents= 3397429600 xhci_hcd 0000:06:00.0: WARN: short transfer on control ep xhci_hcd 0000:06:00.0: Waiting for status stage event xhci_hcd 0000:06:00.0: Event ring deq = 0xca80a550 (DMA) xhci_hcd 0000:06:00.0: xhci_handle_event - returned from handle_tx_event xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90000068638, 64'hca80a558, 4'hf); xhci_hcd 0000:06:00.0: op reg status = 00000008 xhci_hcd 0000:06:00.0: Event ring dequeue ptr: xhci_hcd 0000:06:00.0: @ca80a550 ca80a970 00000000 01000000 01018001 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068024, 32'h8, 4'hf); xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: xhci_handle_event - OS owns TRB xhci_hcd 0000:06:00.0: xhci_handle_event - calling handle_tx_event xhci_hcd 0000:06:00.0: handle_tx_event - ep index = 0 xhci_hcd 0000:06:00.0: DMA address or buffer contents= 3397429616 xhci_hcd 0000:06:00.0: Successful control transfer! xhci_hcd 0000:06:00.0: Ring deq = 0xca80a960 (DMA) xhci_hcd 0000:06:00.0: Ring deq = 0xca80a970 (DMA) xhci_hcd 0000:06:00.0: Ring deq = 0xca80a980 (DMA) xhci_hcd 0000:06:00.0: Event ring deq = 0xca80a560 (DMA) xhci_hcd 0000:06:00.0: Giveback URB ffff8801f56243c0, len = 4, status = 0 xhci_hcd 0000:06:00.0: xhci_handle_event - returned from handle_tx_event xhci_hcd 0000:06:00.0: In xhci_handle_event usb 5-2: default language 0x0409 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90000068638, 64'hca80a568, 4'hf); xhci_hcd 0000:06:00.0: Queueing ctrl tx for slot id 1, ep 0 xhci_hcd 0000:06:00.0: Endpoint state = 0x1 xhci_hcd 0000:06:00.0: Ring enq = 0xca80a990 (DMA) xhci_hcd 0000:06:00.0: Ring enq = 0xca80a9a0 (DMA) xhci_hcd 0000:06:00.0: Ring enq = 0xca80a9b0 (DMA) xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068804, 32'h1, 4'hf); xhci_hcd 0000:06:00.0: op reg status = 00000008 xhci_hcd 0000:06:00.0: Event ring dequeue ptr: xhci_hcd 0000:06:00.0: @ca80a560 ca80a990 00000000 0d0000dd 01018001 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068024, 32'h8, 4'hf); xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: xhci_handle_event - OS owns TRB xhci_hcd 0000:06:00.0: xhci_handle_event - calling handle_tx_event xhci_hcd 0000:06:00.0: handle_tx_event - ep index = 0 xhci_hcd 0000:06:00.0: DMA address or buffer contents= 3397429648 xhci_hcd 0000:06:00.0: WARN: short transfer on control ep xhci_hcd 0000:06:00.0: Waiting for status stage event xhci_hcd 0000:06:00.0: Event ring deq = 0xca80a570 (DMA) xhci_hcd 0000:06:00.0: xhci_handle_event - returned from handle_tx_event xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90000068638, 64'hca80a578, 4'hf); xhci_hcd 0000:06:00.0: op reg status = 00000008 xhci_hcd 0000:06:00.0: Event ring dequeue ptr: xhci_hcd 0000:06:00.0: @ca80a570 ca80a9a0 00000000 01000000 01018001 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068024, 32'h8, 4'hf); xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: xhci_handle_event - OS owns TRB xhci_hcd 0000:06:00.0: xhci_handle_event - calling handle_tx_event xhci_hcd 0000:06:00.0: handle_tx_event - ep index = 0 xhci_hcd 0000:06:00.0: DMA address or buffer contents= 3397429664 xhci_hcd 0000:06:00.0: Successful control transfer! xhci_hcd 0000:06:00.0: Ring deq = 0xca80a990 (DMA) xhci_hcd 0000:06:00.0: Ring deq = 0xca80a9a0 (DMA) xhci_hcd 0000:06:00.0: Ring deq = 0xca80a9b0 (DMA) xhci_hcd 0000:06:00.0: Event ring deq = 0xca80a580 (DMA) xhci_hcd 0000:06:00.0: Giveback URB ffff8801f5bddd80, len = 34, status = 0 xhci_hcd 0000:06:00.0: xhci_handle_event - returned from handle_tx_event xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90000068638, 64'hca80a588, 4'hf); xhci_hcd 0000:06:00.0: Queueing ctrl tx for slot id 1, ep 0 xhci_hcd 0000:06:00.0: Endpoint state = 0x1 xhci_hcd 0000:06:00.0: Ring enq = 0xca80a9c0 (DMA) xhci_hcd 0000:06:00.0: Ring enq = 0xca80a9d0 (DMA) xhci_hcd 0000:06:00.0: Ring enq = 0xca80a9e0 (DMA) xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068804, 32'h1, 4'hf); xhci_hcd 0000:06:00.0: op reg status = 00000008 xhci_hcd 0000:06:00.0: Event ring dequeue ptr: xhci_hcd 0000:06:00.0: @ca80a580 ca80a9c0 00000000 0d0000ed 01018001 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068024, 32'h8, 4'hf); xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: xhci_handle_event - OS owns TRB xhci_hcd 0000:06:00.0: xhci_handle_event - calling handle_tx_event xhci_hcd 0000:06:00.0: handle_tx_event - ep index = 0 xhci_hcd 0000:06:00.0: DMA address or buffer contents= 3397429696 xhci_hcd 0000:06:00.0: WARN: short transfer on control ep xhci_hcd 0000:06:00.0: Waiting for status stage event xhci_hcd 0000:06:00.0: Event ring deq = 0xca80a590 (DMA) xhci_hcd 0000:06:00.0: xhci_handle_event - returned from handle_tx_event xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90000068638, 64'hca80a598, 4'hf); xhci_hcd 0000:06:00.0: op reg status = 00000008 xhci_hcd 0000:06:00.0: Event ring dequeue ptr: xhci_hcd 0000:06:00.0: @ca80a590 ca80a9d0 00000000 01000000 01018001 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068024, 32'h8, 4'hf); xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: xhci_handle_event - OS owns TRB xhci_hcd 0000:06:00.0: xhci_handle_event - calling handle_tx_event xhci_hcd 0000:06:00.0: handle_tx_event - ep index = 0 xhci_hcd 0000:06:00.0: DMA address or buffer contents= 3397429712 xhci_hcd 0000:06:00.0: Successful control transfer! xhci_hcd 0000:06:00.0: Ring deq = 0xca80a9c0 (DMA) xhci_hcd 0000:06:00.0: Ring deq = 0xca80a9d0 (DMA) xhci_hcd 0000:06:00.0: Ring deq = 0xca80a9e0 (DMA) xhci_hcd 0000:06:00.0: Event ring deq = 0xca80a5a0 (DMA) xhci_hcd 0000:06:00.0: Giveback URB ffff8801f5bddd80, len = 18, status = 0 xhci_hcd 0000:06:00.0: xhci_handle_event - returned from handle_tx_event xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90000068638, 64'hca80a5a8, 4'hf); xhci_hcd 0000:06:00.0: Queueing ctrl tx for slot id 1, ep 0 xhci_hcd 0000:06:00.0: Endpoint state = 0x1 xhci_hcd 0000:06:00.0: Ring enq = 0xca80a9f0 (DMA) xhci_hcd 0000:06:00.0: Ring enq = 0xca80aa00 (DMA) xhci_hcd 0000:06:00.0: Ring enq = 0xca80aa10 (DMA) xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068804, 32'h1, 4'hf); xhci_hcd 0000:06:00.0: op reg status = 00000008 xhci_hcd 0000:06:00.0: Event ring dequeue ptr: xhci_hcd 0000:06:00.0: @ca80a5a0 ca80a9f0 00000000 0d0000e5 01018001 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068024, 32'h8, 4'hf); xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: xhci_handle_event - OS owns TRB xhci_hcd 0000:06:00.0: xhci_handle_event - calling handle_tx_event xhci_hcd 0000:06:00.0: handle_tx_event - ep index = 0 xhci_hcd 0000:06:00.0: DMA address or buffer contents= 3397429744 xhci_hcd 0000:06:00.0: WARN: short transfer on control ep xhci_hcd 0000:06:00.0: Waiting for status stage event xhci_hcd 0000:06:00.0: Event ring deq = 0xca80a5b0 (DMA) xhci_hcd 0000:06:00.0: xhci_handle_event - returned from handle_tx_event xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90000068638, 64'hca80a5b8, 4'hf); xhci_hcd 0000:06:00.0: op reg status = 00000008 xhci_hcd 0000:06:00.0: Event ring dequeue ptr: xhci_hcd 0000:06:00.0: @ca80a5b0 ca80aa00 00000000 01000000 01018001 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068024, 32'h8, 4'hf); xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: xhci_handle_event - OS owns TRB xhci_hcd 0000:06:00.0: xhci_handle_event - calling handle_tx_event xhci_hcd 0000:06:00.0: handle_tx_event - ep index = 0 xhci_hcd 0000:06:00.0: DMA address or buffer contents= 3397429760 xhci_hcd 0000:06:00.0: Successful control transfer! xhci_hcd 0000:06:00.0: Ring deq = 0xca80a9f0 (DMA) xhci_hcd 0000:06:00.0: Ring deq = 0xca80aa00 (DMA) xhci_hcd 0000:06:00.0: Ring deq = 0xca80aa10 (DMA) xhci_hcd 0000:06:00.0: Event ring deq = 0xca80a5c0 (DMA) xhci_hcd 0000:06:00.0: Giveback URB ffff8801f5bddd80, len = 26, status = 0 xhci_hcd 0000:06:00.0: xhci_handle_event - returned from handle_tx_event xhci_hcd 0000:06:00.0: In xhci_handle_event usb 5-2: udev 2, busnum 5, minor = 513 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90000068638, 64'hca80a5c8, 4'hf); usb 5-2: New USB device found, idVendor=046d, idProduct=c06b usb 5-2: New USB device strings: Mfr=1, Product=2, SerialNumber=3 usb 5-2: Product: G700 Laser Mouse usb 5-2: Manufacturer: Logitech usb 5-2: SerialNumber: E52DB3FA0035 usb 5-2: usb_probe_device usb 5-2: configuration #1 chosen from 1 choice xhci_hcd 0000:06:00.0: Allocating ring at ffff88022d6164e0 xhci_hcd 0000:06:00.0: Allocating priv segment structure at ffff88022e630bc0 xhci_hcd 0000:06:00.0: // Allocating segment at ffff8800ca81f000 (virtual) 0xca81f000 (DMA) xhci_hcd 0000:06:00.0: Linking segment 0xca81f000 to segment 0xca81f000 (DMA) xhci_hcd 0000:06:00.0: Wrote link toggle flag to segment ffff88022e630bc0 (virtual), 0xca81f000 (DMA) xhci_hcd 0000:06:00.0: add ep 0x81, slot id 1, new drop flags = 0x0, new add flags = 0x9, new slot info = 0x18100000 xhci_hcd 0000:06:00.0: Allocating ring at ffff88022d616720 xhci_hcd 0000:06:00.0: Allocating priv segment structure at ffff88022e630be0 xhci_hcd 0000:06:00.0: // Allocating segment at ffff8800ca81f400 (virtual) 0xca81f400 (DMA) xhci_hcd 0000:06:00.0: Linking segment 0xca81f400 to segment 0xca81f400 (DMA) xhci_hcd 0000:06:00.0: Wrote link toggle flag to segment ffff88022e630be0 (virtual), 0xca81f400 (DMA) xhci_hcd 0000:06:00.0: add ep 0x82, slot id 1, new drop flags = 0x0, new add flags = 0x29, new slot info = 0x28100000 xhci_hcd 0000:06:00.0: xhci_check_bandwidth called for udev ffff88022a2f0000 xhci_hcd 0000:06:00.0: New Input Control Context: xhci_hcd 0000:06:00.0: @ffff8800ca80e000 (virt) @ca80e000 (dma) 0x000000 - drop flags xhci_hcd 0000:06:00.0: @ffff8800ca80e004 (virt) @ca80e004 (dma) 0x000029 - add flags xhci_hcd 0000:06:00.0: @ffff8800ca80e008 (virt) @ca80e008 (dma) 0x000000 - rsvd2[0] xhci_hcd 0000:06:00.0: @ffff8800ca80e00c (virt) @ca80e00c (dma) 0x000000 - rsvd2[1] xhci_hcd 0000:06:00.0: @ffff8800ca80e010 (virt) @ca80e010 (dma) 0x000000 - rsvd2[2] xhci_hcd 0000:06:00.0: @ffff8800ca80e014 (virt) @ca80e014 (dma) 0x000000 - rsvd2[3] xhci_hcd 0000:06:00.0: @ffff8800ca80e018 (virt) @ca80e018 (dma) 0x000000 - rsvd2[4] xhci_hcd 0000:06:00.0: @ffff8800ca80e01c (virt) @ca80e01c (dma) 0x000000 - rsvd2[5] xhci_hcd 0000:06:00.0: Slot Context: xhci_hcd 0000:06:00.0: @ffff8800ca80e020 (virt) @ca80e020 (dma) 0x28100000 - dev_info xhci_hcd 0000:06:00.0: @ffff8800ca80e024 (virt) @ca80e024 (dma) 0x040000 - dev_info2 xhci_hcd 0000:06:00.0: @ffff8800ca80e028 (virt) @ca80e028 (dma) 0x000000 - tt_info xhci_hcd 0000:06:00.0: @ffff8800ca80e02c (virt) @ca80e02c (dma) 0x000000 - dev_state xhci_hcd 0000:06:00.0: @ffff8800ca80e030 (virt) @ca80e030 (dma) 0x000000 - rsvd[0] xhci_hcd 0000:06:00.0: @ffff8800ca80e034 (virt) @ca80e034 (dma) 0x000000 - rsvd[1] xhci_hcd 0000:06:00.0: @ffff8800ca80e038 (virt) @ca80e038 (dma) 0x000000 - rsvd[2] xhci_hcd 0000:06:00.0: @ffff8800ca80e03c (virt) @ca80e03c (dma) 0x000000 - rsvd[3] xhci_hcd 0000:06:00.0: Endpoint 00 Context: xhci_hcd 0000:06:00.0: @ffff8800ca80e040 (virt) @ca80e040 (dma) 0x000001 - ep_info xhci_hcd 0000:06:00.0: @ffff8800ca80e044 (virt) @ca80e044 (dma) 0x200026 - ep_info2 xhci_hcd 0000:06:00.0: @ffff8800ca80e048 (virt) @ca80e048 (dma) 0xca80a801 - deq xhci_hcd 0000:06:00.0: @ffff8800ca80e050 (virt) @ca80e050 (dma) 0x000000 - tx_info xhci_hcd 0000:06:00.0: @ffff8800ca80e054 (virt) @ca80e054 (dma) 0x000000 - rsvd[0] xhci_hcd 0000:06:00.0: @ffff8800ca80e058 (virt) @ca80e058 (dma) 0x000000 - rsvd[1] xhci_hcd 0000:06:00.0: @ffff8800ca80e05c (virt) @ca80e05c (dma) 0x000000 - rsvd[2] xhci_hcd 0000:06:00.0: Endpoint 01 Context: xhci_hcd 0000:06:00.0: @ffff8800ca80e060 (virt) @ca80e060 (dma) 0x000000 - ep_info xhci_hcd 0000:06:00.0: @ffff8800ca80e064 (virt) @ca80e064 (dma) 0x000000 - ep_info2 xhci_hcd 0000:06:00.0: @ffff8800ca80e068 (virt) @ca80e068 (dma) 0x000000 - deq xhci_hcd 0000:06:00.0: @ffff8800ca80e070 (virt) @ca80e070 (dma) 0x000000 - tx_info xhci_hcd 0000:06:00.0: @ffff8800ca80e074 (virt) @ca80e074 (dma) 0x000000 - rsvd[0] xhci_hcd 0000:06:00.0: @ffff8800ca80e078 (virt) @ca80e078 (dma) 0x000000 - rsvd[1] xhci_hcd 0000:06:00.0: @ffff8800ca80e07c (virt) @ca80e07c (dma) 0x000000 - rsvd[2] xhci_hcd 0000:06:00.0: Endpoint 02 Context: xhci_hcd 0000:06:00.0: @ffff8800ca80e080 (virt) @ca80e080 (dma) 0x000000 - ep_info xhci_hcd 0000:06:00.0: @ffff8800ca80e084 (virt) @ca80e084 (dma) 0x08003e - ep_info2 xhci_hcd 0000:06:00.0: @ffff8800ca80e088 (virt) @ca80e088 (dma) 0xca81f001 - deq xhci_hcd 0000:06:00.0: @ffff8800ca80e090 (virt) @ca80e090 (dma) 0x080008 - tx_info xhci_hcd 0000:06:00.0: @ffff8800ca80e094 (virt) @ca80e094 (dma) 0x000000 - rsvd[0] xhci_hcd 0000:06:00.0: @ffff8800ca80e098 (virt) @ca80e098 (dma) 0x000000 - rsvd[1] xhci_hcd 0000:06:00.0: @ffff8800ca80e09c (virt) @ca80e09c (dma) 0x000000 - rsvd[2] xhci_hcd 0000:06:00.0: Endpoint 03 Context: xhci_hcd 0000:06:00.0: @ffff8800ca80e0a0 (virt) @ca80e0a0 (dma) 0x000000 - ep_info xhci_hcd 0000:06:00.0: @ffff8800ca80e0a4 (virt) @ca80e0a4 (dma) 0x000000 - ep_info2 xhci_hcd 0000:06:00.0: @ffff8800ca80e0a8 (virt) @ca80e0a8 (dma) 0x000000 - deq xhci_hcd 0000:06:00.0: @ffff8800ca80e0b0 (virt) @ca80e0b0 (dma) 0x000000 - tx_info xhci_hcd 0000:06:00.0: @ffff8800ca80e0b4 (virt) @ca80e0b4 (dma) 0x000000 - rsvd[0] xhci_hcd 0000:06:00.0: @ffff8800ca80e0b8 (virt) @ca80e0b8 (dma) 0x000000 - rsvd[1] xhci_hcd 0000:06:00.0: @ffff8800ca80e0bc (virt) @ca80e0bc (dma) 0x000000 - rsvd[2] xhci_hcd 0000:06:00.0: Endpoint 04 Context: xhci_hcd 0000:06:00.0: @ffff8800ca80e0c0 (virt) @ca80e0c0 (dma) 0x000000 - ep_info xhci_hcd 0000:06:00.0: @ffff8800ca80e0c4 (virt) @ca80e0c4 (dma) 0x14003e - ep_info2 xhci_hcd 0000:06:00.0: @ffff8800ca80e0c8 (virt) @ca80e0c8 (dma) 0xca81f401 - deq xhci_hcd 0000:06:00.0: @ffff8800ca80e0d0 (virt) @ca80e0d0 (dma) 0x140014 - tx_info xhci_hcd 0000:06:00.0: @ffff8800ca80e0d4 (virt) @ca80e0d4 (dma) 0x000000 - rsvd[0] xhci_hcd 0000:06:00.0: @ffff8800ca80e0d8 (virt) @ca80e0d8 (dma) 0x000000 - rsvd[1] xhci_hcd 0000:06:00.0: @ffff8800ca80e0dc (virt) @ca80e0dc (dma) 0x000000 - rsvd[2] xhci_hcd 0000:06:00.0: Endpoint state = 0x1 xhci_hcd 0000:06:00.0: Command ring enq = 0xca80a0c0 (DMA) xhci_hcd 0000:06:00.0: // Ding dong! xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068800, 32'h0, 4'hf); xhci_hcd 0000:06:00.0: op reg status = 00000008 xhci_hcd 0000:06:00.0: Event ring dequeue ptr: xhci_hcd 0000:06:00.0: @ca80a5c0 ca80a0b0 00000000 11000000 01008401 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90000068024, 32'h8, 4'hf); xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: xhci_handle_event - OS owns TRB xhci_hcd 0000:06:00.0: xhci_handle_event - calling handle_cmd_completion xhci_hcd 0000:06:00.0: Completed config ep cmd xhci_hcd 0000:06:00.0: Command ring deq = 0xca80a0c0 (DMA) xhci_hcd 0000:06:00.0: xhci_handle_event - returned from handle_cmd_completion xhci_hcd 0000:06:00.0: ERROR: unexpected command completion code 0x11. xhci_hcd 0000:06:00.0: Event ring deq = 0xca80a5d0 (DMA) xhci_hcd 0000:06:00.0: xhci_reset_bandwidth called for udev ffff88022a2f0000 xhci_hcd 0000:06:00.0: In xhci_handle_event xhci_hcd 0000:06:00.0: Freeing ring at ffff88022d6164e0 xhci_hcd 0000:06:00.0: Freeing DMA segment at ffff8800ca81f000 (virtual) 0xca81f000 (DMA) xhci_hcd 0000:06:00.0: Freeing priv segment structure at ffff88022e630bc0 xhci_hcd 0000:06:00.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90000068638, 64'hca80a5d8, 4'hf); xhci_hcd 0000:06:00.0: Freeing ring at ffff88022d616720 xhci_hcd 0000:06:00.0: Freeing DMA segment at ffff8800ca81f400 (virtual) 0xca81f400 (DMA) xhci_hcd 0000:06:00.0: Freeing priv segment structure at ffff88022e630be0 usb 5-2: can't set config #1, error -22 drivers/usb/core/inode.c: creating file '002'