15:02:31 15:02:31 // reboot trx 3 15:02:31 0A: 00000004 15:02:31 02: 00000001 15:02:31 02: 00019000 15:02:31 0A: 000000FF 15:02:34 15:02:34 // chmod 3 cnt 15:02:34 0A: 00000004 15:02:34 02: 00000001 15:02:34 02: 00039100 15:02:34 0A: 000000FF 15:02:37 15:02:37 // chmod 3 cnt 15:02:37 0A: 00000004 15:02:37 02: 00000001 15:02:37 02: 00039100 15:02:37 0A: 000000FF 15:02:37 15:02:37 // chmod 3 cnt 15:02:37 0A: 00000004 15:02:37 02: 00000001 15:02:37 02: 00039100 15:02:37 0A: 000000FF 15:02:37 15:02:37 // chmod 3 cnt 15:02:37 0A: 00000004 15:02:37 02: 00000001 15:02:37 02: 00039100 15:02:37 0A: 000000FF 15:02:41 15:02:41 // reset mcu 15:02:41 16: 023C3460 15:02:41 17: 00000001 15:02:41 15:02:41 // encoder limit 100 15:02:41 11: 00000064 15:02:41 15:02:41 // encoder virt rate 136691 15:02:41 10: 000215F3 15:02:41 15:02:41 // trx mask 00100000 15:02:41 0A: 00000004 15:02:41 15:02:41 // sched write 0 adc_sample_time freq 62 15:02:41 08: 0000003E 15:02:41 08: 00025000 15:02:41 15:02:41 // sched write 0 adc_sample_time sw 62 15:02:41 08: 0000003E 15:02:41 08: 00029000 15:02:41 15:02:41 // sched write 0 timeout freq 4250 15:02:41 08: 0000109A 15:02:41 08: 0000D000 15:02:41 15:02:41 // sched write 0 timeout freqmaxtomin 11250 15:02:41 08: 00002BF2 15:02:41 08: 00035000 15:02:41 15:02:41 // sched write 0 timeout sw 324 15:02:41 08: 00000144 15:02:41 08: 00011000 15:02:41 15:02:41 // pll write 0 tx 2 2 lo 2 2 15:02:41 08: 02000002 15:02:41 08: 00015000 15:02:41 08: 12000002 15:02:41 08: 00015000 15:02:41 15:02:41 // pll write 0 tx 3 70 lo 3 70 15:02:41 08: 03000046 15:02:41 08: 00015000 15:02:41 08: 13000046 15:02:41 08: 00015000 15:02:41 15:02:41 // pll write 0 tx 4 0 lo 4 2090000 15:02:41 08: 04000000 15:02:41 08: 00015000 15:02:41 08: 141FE410 15:02:41 08: 00015000 15:02:41 15:02:41 // pll write 0 tx 5 0 lo 5 0 15:02:41 08: 05000000 15:02:41 08: 00015000 15:02:41 08: 15000000 15:02:41 08: 00015000 15:02:41 15:02:41 // pll write 0 tx 6 265863 lo 6 265863 15:02:41 08: 06040E87 15:02:41 08: 00015000 15:02:41 08: 16040E87 15:02:41 08: 00015000 15:02:41 15:02:41 // pll write 0 tx 7 1049850 lo 7 1049850 15:02:41 08: 071004FA 15:02:41 08: 00015000 15:02:41 08: 171004FA 15:02:41 08: 00015000 15:02:41 15:02:41 // pll write 0 tx 8 12799 lo 8 12799 15:02:41 08: 080031FF 15:02:41 08: 00015000 15:02:41 08: 180031FF 15:02:41 08: 00015000 15:02:41 15:02:41 // pll write 0 tx 9 2359308 lo 9 2359308 15:02:41 08: 0924000C 15:02:41 08: 00015000 15:02:41 08: 1924000C 15:02:41 08: 00015000 15:02:41 15:02:41 // pll write 0 tx 10 0 lo 10 0 15:02:41 08: 0A000000 15:02:41 08: 00015000 15:02:41 08: 1A000000 15:02:41 08: 00015000 15:02:41 15:02:41 // pll write 0 tx 11 2168 lo 11 2168 15:02:41 08: 0B000878 15:02:41 08: 00015000 15:02:41 08: 1B000878 15:02:41 08: 00015000 15:02:41 15:02:41 // pll write 0 tx 13 1 lo 13 1 15:02:41 08: 0D000001 15:02:41 08: 00015000 15:02:41 08: 1D000001 15:02:41 08: 00015000 15:02:41 15:02:41 // freq write 0 limit 101 15:02:41 08: 00000065 15:02:41 08: 00021000 15:02:41 15:02:41 // freq write 0 vectors_total 1 15:02:41 08: 00000001 15:02:41 08: 0002D000 15:02:41 15:02:41 // freq write 3 span 0 [13500:50:18500] [13525:50:18525] MHz 15:02:41 0A: 00000004 15:02:41 02: 24A9A700 15:02:41 02: 00001003 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 02FAF080 15:02:41 02: 00001008 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 4EAF9900 15:02:41 02: 00001014 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 26271F40 15:02:41 02: 00001803 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 02FAF080 15:02:41 02: 00001808 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 502D1140 15:02:41 02: 00001814 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 vga 0 rx 36 lo 36 15:02:41 0A: 00000004 15:02:41 02: 00000024 15:02:41 02: 00005000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 00200024 15:02:41 02: 00005000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 0 tx 1 rx 13 15:02:41 0A: 00000004 15:02:41 02: 00000001 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 0000040D 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 1 tx 1 rx 12 15:02:41 0A: 00000004 15:02:41 02: 00000011 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 0000041C 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 2 tx 2 rx 13 15:02:41 0A: 00000004 15:02:41 02: 00000022 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 0000042D 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 3 tx 2 rx 12 15:02:41 0A: 00000004 15:02:41 02: 00000032 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 0000043C 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 4 tx 3 rx 13 15:02:41 0A: 00000004 15:02:41 02: 00000043 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 0000044D 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 5 tx 3 rx 12 15:02:41 0A: 00000004 15:02:41 02: 00000053 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 0000045C 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 6 tx 4 rx 13 15:02:41 0A: 00000004 15:02:41 02: 00000064 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 0000046D 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 7 tx 4 rx 12 15:02:41 0A: 00000004 15:02:41 02: 00000074 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 0000047C 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 8 tx 3 rx 11 15:02:41 0A: 00000004 15:02:41 02: 00000083 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 0000048B 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 9 tx 3 rx 10 15:02:41 0A: 00000004 15:02:41 02: 00000093 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 0000049A 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 10 tx 4 rx 11 15:02:41 0A: 00000004 15:02:41 02: 000000A4 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 000004AB 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 11 tx 4 rx 10 15:02:41 0A: 00000004 15:02:41 02: 000000B4 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 000004BA 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 12 tx 5 rx 11 15:02:41 0A: 00000004 15:02:41 02: 000000C5 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 000004CB 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 13 tx 5 rx 10 15:02:41 0A: 00000004 15:02:41 02: 000000D5 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 000004DA 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 14 tx 6 rx 11 15:02:41 0A: 00000004 15:02:41 02: 000000E6 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 000004EB 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 15 tx 6 rx 10 15:02:41 0A: 00000004 15:02:41 02: 000000F6 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 000004FA 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 16 tx 5 rx 9 15:02:41 0A: 00000004 15:02:41 02: 00000105 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 00000509 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 17 tx 5 rx 8 15:02:41 0A: 00000004 15:02:41 02: 00000115 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 00000518 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 18 tx 6 rx 9 15:02:41 0A: 00000004 15:02:41 02: 00000126 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 00000529 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 19 tx 6 rx 8 15:02:41 0A: 00000004 15:02:41 02: 00000136 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 00000538 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 20 tx 7 rx 9 15:02:41 0A: 00000004 15:02:41 02: 00000147 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 00000549 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 21 tx 7 rx 8 15:02:41 0A: 00000004 15:02:41 02: 00000157 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 00000558 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 22 tx 8 rx 9 15:02:41 0A: 00000004 15:02:41 02: 00000168 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 00000569 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 23 tx 8 rx 8 15:02:41 0A: 00000004 15:02:41 02: 00000178 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 00000578 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 24 tx 7 rx 7 15:02:41 0A: 00000004 15:02:41 02: 00000187 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 00000587 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 25 tx 7 rx 6 15:02:41 0A: 00000004 15:02:41 02: 00000197 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 00000596 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 26 tx 8 rx 7 15:02:41 0A: 00000004 15:02:41 02: 000001A8 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 000005A7 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 27 tx 8 rx 6 15:02:41 0A: 00000004 15:02:41 02: 000001B8 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 000005B6 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 28 tx 9 rx 7 15:02:41 0A: 00000004 15:02:41 02: 000001C9 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 000005C7 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 29 tx 9 rx 6 15:02:41 0A: 00000004 15:02:41 02: 000001D9 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 000005D6 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 30 tx 10 rx 7 15:02:41 0A: 00000004 15:02:41 02: 000001EA 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 000005E7 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 31 tx 10 rx 6 15:02:41 0A: 00000004 15:02:41 02: 000001FA 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 000005F6 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 32 tx 9 rx 5 15:02:41 0A: 00000004 15:02:41 02: 00000209 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 00000605 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 33 tx 9 rx 4 15:02:41 0A: 00000004 15:02:41 02: 00000219 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 00000614 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 34 tx 10 rx 5 15:02:41 0A: 00000004 15:02:41 02: 0000022A 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 00000625 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 35 tx 10 rx 4 15:02:41 0A: 00000004 15:02:41 02: 0000023A 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 00000634 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 36 tx 11 rx 5 15:02:41 0A: 00000004 15:02:41 02: 0000024B 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 00000645 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 37 tx 11 rx 4 15:02:41 0A: 00000004 15:02:41 02: 0000025B 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 00000654 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 38 tx 12 rx 5 15:02:41 0A: 00000004 15:02:41 02: 0000026C 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 00000665 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 39 tx 12 rx 4 15:02:41 0A: 00000004 15:02:41 02: 0000027C 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 00000674 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 40 tx 11 rx 3 15:02:41 0A: 00000004 15:02:41 02: 0000028B 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 00000683 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 41 tx 11 rx 2 15:02:41 0A: 00000004 15:02:41 02: 0000029B 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 00000692 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 42 tx 12 rx 3 15:02:41 0A: 00000004 15:02:41 02: 000002AC 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 000006A3 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 43 tx 12 rx 2 15:02:41 0A: 00000004 15:02:41 02: 000002BC 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 000006B2 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 44 tx 13 rx 3 15:02:41 0A: 00000004 15:02:41 02: 000002CD 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 000006C3 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 45 tx 13 rx 2 15:02:41 0A: 00000004 15:02:41 02: 000002DD 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 000006D2 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 46 tx 14 rx 3 15:02:41 0A: 00000004 15:02:41 02: 000002EE 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 000006E3 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 47 tx 14 rx 2 15:02:41 0A: 00000004 15:02:41 02: 000002FE 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 000006F2 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 48 tx 0 rx 15 15:02:41 0A: 00000004 15:02:41 02: 00000300 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 0000070F 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // ram write 3 sw 49 tx 15 rx 0 15:02:41 0A: 00000004 15:02:41 02: 0000031F 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 0A: 00000004 15:02:41 02: 00000710 15:02:41 02: 00009000 15:02:41 0A: 00000004 15:02:41 15:02:41 // reset seq 15:02:41 08: 00000001 15:02:41 08: 00031000 15:02:41 0E: 00000001 15:02:41 0E: 00000000 15:02:41 15:02:41 // start 15:02:41 0E: 0000000C 15:02:41 0C: 00000001 15:15:50 15:15:50 // reset mcu 15:15:50 16: 023C3460 15:15:50 17: 00000001 15:15:50 15:15:50 // encoder limit 100 15:15:50 11: 00000064 15:15:50 15:15:50 // encoder virt rate 136691 15:15:50 10: 000215F3 15:15:50 15:15:50 // trx mask 00100000 15:15:50 0A: 00000004 15:15:50 15:15:50 // sched write 0 adc_sample_time freq 62 15:15:50 08: 0000003E 15:15:50 08: 00025000 15:15:50 15:15:50 // sched write 0 adc_sample_time sw 62 15:15:50 08: 0000003E 15:15:50 08: 00029000 15:15:50 15:15:50 // sched write 0 timeout freq 4250 15:15:50 08: 0000109A 15:15:50 08: 0000D000 15:15:50 15:15:50 // sched write 0 timeout freqmaxtomin 11250 15:15:50 08: 00002BF2 15:15:50 08: 00035000 15:15:50 15:15:50 // sched write 0 timeout sw 324 15:15:50 08: 00000144 15:15:50 08: 00011000 15:15:50 15:15:50 // pll write 0 tx 2 2 lo 2 2 15:15:50 08: 02000002 15:15:50 08: 00015000 15:15:50 08: 12000002 15:15:50 08: 00015000 15:15:50 15:15:50 // pll write 0 tx 3 70 lo 3 70 15:15:50 08: 03000046 15:15:50 08: 00015000 15:15:50 08: 13000046 15:15:50 08: 00015000 15:15:50 15:15:50 // pll write 0 tx 4 0 lo 4 2090000 15:15:50 08: 04000000 15:15:50 08: 00015000 15:15:50 08: 141FE410 15:15:50 08: 00015000 15:15:50 15:15:50 // pll write 0 tx 5 0 lo 5 0 15:15:50 08: 05000000 15:15:50 08: 00015000 15:15:50 08: 15000000 15:15:50 08: 00015000 15:15:50 15:15:50 // pll write 0 tx 6 265863 lo 6 265863 15:15:50 08: 06040E87 15:15:50 08: 00015000 15:15:50 08: 16040E87 15:15:50 08: 00015000 15:15:50 15:15:50 // pll write 0 tx 7 1049850 lo 7 1049850 15:15:50 08: 071004FA 15:15:50 08: 00015000 15:15:50 08: 171004FA 15:15:50 08: 00015000 15:15:50 15:15:50 // pll write 0 tx 8 12799 lo 8 12799 15:15:50 08: 080031FF 15:15:50 08: 00015000 15:15:50 08: 180031FF 15:15:50 08: 00015000 15:15:50 15:15:50 // pll write 0 tx 9 2359308 lo 9 2359308 15:15:50 08: 0924000C 15:15:50 08: 00015000 15:15:50 08: 1924000C 15:15:50 08: 00015000 15:15:50 15:15:50 // pll write 0 tx 10 0 lo 10 0 15:15:50 08: 0A000000 15:15:50 08: 00015000 15:15:50 08: 1A000000 15:15:50 08: 00015000 15:15:50 15:15:50 // pll write 0 tx 11 2168 lo 11 2168 15:15:50 08: 0B000878 15:15:50 08: 00015000 15:15:50 08: 1B000878 15:15:50 08: 00015000 15:15:50 15:15:50 // pll write 0 tx 13 1 lo 13 1 15:15:50 08: 0D000001 15:15:50 08: 00015000 15:15:50 08: 1D000001 15:15:50 08: 00015000 15:15:50 15:15:50 // freq write 0 limit 101 15:15:50 08: 00000065 15:15:50 08: 00021000 15:15:50 15:15:50 // freq write 0 vectors_total 1 15:15:50 08: 00000001 15:15:50 08: 0002D000 15:15:50 15:15:50 // freq write 3 span 0 [13500:50:18500] [13525:50:18525] MHz 15:15:50 0A: 00000004 15:15:50 02: 24A9A700 15:15:50 02: 00001003 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 02FAF080 15:15:50 02: 00001008 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 4EAF9900 15:15:50 02: 00001014 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 26271F40 15:15:50 02: 00001803 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 02FAF080 15:15:50 02: 00001808 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 502D1140 15:15:50 02: 00001814 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 00000001 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 0000040D 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 0 tx 1 rx 13 15:15:50 0A: 00000004 15:15:50 02: 00000001 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 0000040D 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 1 tx 1 rx 12 15:15:50 0A: 00000004 15:15:50 02: 00000011 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 0000041C 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 2 tx 2 rx 13 15:15:50 0A: 00000004 15:15:50 02: 00000022 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 0000042D 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 3 tx 2 rx 12 15:15:50 0A: 00000004 15:15:50 02: 00000032 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 0000043C 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 4 tx 3 rx 13 15:15:50 0A: 00000004 15:15:50 02: 00000043 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 0000044D 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 5 tx 3 rx 12 15:15:50 0A: 00000004 15:15:50 02: 00000053 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 0000045C 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 6 tx 4 rx 13 15:15:50 0A: 00000004 15:15:50 02: 00000064 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 0000046D 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 7 tx 4 rx 12 15:15:50 0A: 00000004 15:15:50 02: 00000074 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 0000047C 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 8 tx 3 rx 11 15:15:50 0A: 00000004 15:15:50 02: 00000083 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 0000048B 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 9 tx 3 rx 10 15:15:50 0A: 00000004 15:15:50 02: 00000093 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 0000049A 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 000000B4 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 000004BA 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 11 tx 4 rx 10 15:15:50 0A: 00000004 15:15:50 02: 000000B4 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 000004BA 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 12 tx 5 rx 11 15:15:50 0A: 00000004 15:15:50 02: 000000C5 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 000004CB 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 13 tx 5 rx 10 15:15:50 0A: 00000004 15:15:50 02: 000000D5 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 000004DA 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 14 tx 6 rx 11 15:15:50 0A: 00000004 15:15:50 02: 000000E6 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 000004EB 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 15 tx 6 rx 10 15:15:50 0A: 00000004 15:15:50 02: 000000F6 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 000004FA 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 16 tx 5 rx 9 15:15:50 0A: 00000004 15:15:50 02: 00000105 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 00000509 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 17 tx 5 rx 8 15:15:50 0A: 00000004 15:15:50 02: 00000115 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 00000518 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 18 tx 6 rx 9 15:15:50 0A: 00000004 15:15:50 02: 00000126 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 00000529 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 19 tx 6 rx 8 15:15:50 0A: 00000004 15:15:50 02: 00000136 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 00000538 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 20 tx 7 rx 9 15:15:50 0A: 00000004 15:15:50 02: 00000147 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 00000549 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 21 tx 7 rx 8 15:15:50 0A: 00000004 15:15:50 02: 00000157 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 00000558 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 22 tx 8 rx 9 15:15:50 0A: 00000004 15:15:50 02: 00000168 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 00000569 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 23 tx 8 rx 8 15:15:50 0A: 00000004 15:15:50 02: 00000178 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 00000578 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 24 tx 7 rx 7 15:15:50 0A: 00000004 15:15:50 02: 00000187 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 00000587 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 25 tx 7 rx 6 15:15:50 0A: 00000004 15:15:50 02: 00000197 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 00000596 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 26 tx 8 rx 7 15:15:50 0A: 00000004 15:15:50 02: 000001A8 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 000005A7 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 27 tx 8 rx 6 15:15:50 0A: 00000004 15:15:50 02: 000001B8 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 000005B6 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 28 tx 9 rx 7 15:15:50 0A: 00000004 15:15:50 02: 000001C9 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 000005C7 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 29 tx 9 rx 6 15:15:50 0A: 00000004 15:15:50 02: 000001D9 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 000005D6 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 30 tx 10 rx 7 15:15:50 0A: 00000004 15:15:50 02: 000001EA 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 000005E7 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 31 tx 10 rx 6 15:15:50 0A: 00000004 15:15:50 02: 000001FA 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 000005F6 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 32 tx 9 rx 5 15:15:50 0A: 00000004 15:15:50 02: 00000209 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 00000605 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 33 tx 9 rx 4 15:15:50 0A: 00000004 15:15:50 02: 00000219 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 00000614 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 34 tx 10 rx 5 15:15:50 0A: 00000004 15:15:50 02: 0000022A 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 00000625 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 35 tx 10 rx 4 15:15:50 0A: 00000004 15:15:50 02: 0000023A 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 00000634 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 36 tx 11 rx 5 15:15:50 0A: 00000004 15:15:50 02: 0000024B 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 00000645 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 37 tx 11 rx 4 15:15:50 0A: 00000004 15:15:50 02: 0000025B 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 00000654 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 38 tx 12 rx 5 15:15:50 0A: 00000004 15:15:50 02: 0000026C 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 00000665 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 39 tx 12 rx 4 15:15:50 0A: 00000004 15:15:50 02: 0000027C 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 00000674 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 40 tx 11 rx 3 15:15:50 0A: 00000004 15:15:50 02: 0000028B 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 00000683 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 41 tx 11 rx 2 15:15:50 0A: 00000004 15:15:50 02: 0000029B 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 00000692 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 42 tx 12 rx 3 15:15:50 0A: 00000004 15:15:50 02: 000002AC 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 000006A3 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 43 tx 12 rx 2 15:15:50 0A: 00000004 15:15:50 02: 000002BC 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 000006B2 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 44 tx 13 rx 3 15:15:50 0A: 00000004 15:15:50 02: 000002CD 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 000006C3 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 45 tx 13 rx 2 15:15:50 0A: 00000004 15:15:50 02: 000002DD 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 000006D2 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 46 tx 14 rx 3 15:15:50 0A: 00000004 15:15:50 02: 000002EE 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 000006E3 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 47 tx 14 rx 2 15:15:50 0A: 00000004 15:15:50 02: 000002FE 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 000006F2 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 48 tx 0 rx 15 15:15:50 0A: 00000004 15:15:50 02: 00000300 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 0000070F 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // ram write 3 sw 49 tx 15 rx 0 15:15:50 0A: 00000004 15:15:50 02: 0000031F 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 0A: 00000004 15:15:50 02: 00000710 15:15:50 02: 00009000 15:15:50 0A: 00000004 15:15:50 15:15:50 // reset seq 15:15:50 08: 00000001 15:15:50 08: 00031000 15:15:50 0E: 00000001 15:15:50 0E: 00000000 15:15:50 15:15:50 // start 15:15:50 0E: 0000000C 15:15:50 0C: 00000001 15:16:02 15:16:02 // chmod 3 cnt 15:16:02 0A: 00000004 15:16:02 02: 00000001 15:16:02 02: 00039100 15:16:02 0A: 000000FF 15:16:05 15:16:05 // reset mcu 15:16:05 16: 023C3460 15:16:05 17: 00000001 15:16:05 15:16:05 // encoder limit 100 15:16:05 11: 00000064 15:16:05 15:16:05 // encoder virt rate 136691 15:16:05 10: 000215F3 15:16:05 15:16:05 // trx mask 00100000 15:16:05 0A: 00000004 15:16:05 15:16:05 // sched write 0 adc_sample_time freq 62 15:16:05 08: 0000003E 15:16:05 08: 00025000 15:16:05 15:16:05 // sched write 0 adc_sample_time sw 62 15:16:05 08: 0000003E 15:16:05 08: 00029000 15:16:05 15:16:05 // sched write 0 timeout freq 4250 15:16:05 08: 0000109A 15:16:05 08: 0000D000 15:16:05 15:16:05 // sched write 0 timeout freqmaxtomin 11250 15:16:05 08: 00002BF2 15:16:05 08: 00035000 15:16:05 15:16:05 // sched write 0 timeout sw 324 15:16:05 08: 00000144 15:16:05 08: 00011000 15:16:05 15:16:05 // pll write 0 tx 2 2 lo 2 2 15:16:05 08: 02000002 15:16:05 08: 00015000 15:16:05 08: 12000002 15:16:05 08: 00015000 15:16:05 15:16:05 // pll write 0 tx 3 70 lo 3 70 15:16:05 08: 03000046 15:16:05 08: 00015000 15:16:05 08: 13000046 15:16:05 08: 00015000 15:16:05 15:16:05 // pll write 0 tx 4 0 lo 4 2090000 15:16:05 08: 04000000 15:16:05 08: 00015000 15:16:05 08: 141FE410 15:16:05 08: 00015000 15:16:05 15:16:05 // pll write 0 tx 5 0 lo 5 0 15:16:05 08: 05000000 15:16:05 08: 00015000 15:16:05 08: 15000000 15:16:05 08: 00015000 15:16:05 15:16:05 // pll write 0 tx 6 265863 lo 6 265863 15:16:05 08: 06040E87 15:16:05 08: 00015000 15:16:05 08: 16040E87 15:16:05 08: 00015000 15:16:05 15:16:05 // pll write 0 tx 7 1049850 lo 7 1049850 15:16:05 08: 071004FA 15:16:05 08: 00015000 15:16:05 08: 171004FA 15:16:05 08: 00015000 15:16:05 15:16:05 // pll write 0 tx 8 12799 lo 8 12799 15:16:05 08: 080031FF 15:16:05 08: 00015000 15:16:05 08: 180031FF 15:16:05 08: 00015000 15:16:05 15:16:05 // pll write 0 tx 9 2359308 lo 9 2359308 15:16:05 08: 0924000C 15:16:05 08: 00015000 15:16:05 08: 1924000C 15:16:05 08: 00015000 15:16:05 15:16:05 // pll write 0 tx 10 0 lo 10 0 15:16:05 08: 0A000000 15:16:05 08: 00015000 15:16:05 08: 1A000000 15:16:05 08: 00015000 15:16:05 15:16:05 // pll write 0 tx 11 2168 lo 11 2168 15:16:05 08: 0B000878 15:16:05 08: 00015000 15:16:05 08: 1B000878 15:16:05 08: 00015000 15:16:05 15:16:05 // pll write 0 tx 13 1 lo 13 1 15:16:05 08: 0D000001 15:16:05 08: 00015000 15:16:05 08: 1D000001 15:16:05 08: 00015000 15:16:05 15:16:05 // freq write 0 limit 101 15:16:05 08: 00000065 15:16:05 08: 00021000 15:16:05 15:16:05 // freq write 0 vectors_total 1 15:16:05 08: 00000001 15:16:05 08: 0002D000 15:16:05 15:16:05 // freq write 3 span 0 [13500:50:18500] [13525:50:18525] MHz 15:16:05 0A: 00000004 15:16:05 02: 24A9A700 15:16:05 02: 00001003 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 02FAF080 15:16:05 02: 00001008 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 4EAF9900 15:16:05 02: 00001014 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 26271F40 15:16:05 02: 00001803 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 02FAF080 15:16:05 02: 00001808 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 502D1140 15:16:05 02: 00001814 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 vga 0 rx 36 lo 36 15:16:05 0A: 00000004 15:16:05 02: 00000024 15:16:05 02: 00005000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 00200024 15:16:05 02: 00005000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 0 tx 1 rx 13 15:16:05 0A: 00000004 15:16:05 02: 00000001 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 0000040D 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 1 tx 1 rx 12 15:16:05 0A: 00000004 15:16:05 02: 00000011 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 0000041C 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 2 tx 2 rx 13 15:16:05 0A: 00000004 15:16:05 02: 00000022 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 0000042D 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 3 tx 2 rx 12 15:16:05 0A: 00000004 15:16:05 02: 00000032 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 0000043C 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 4 tx 3 rx 13 15:16:05 0A: 00000004 15:16:05 02: 00000043 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 0000044D 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 5 tx 3 rx 12 15:16:05 0A: 00000004 15:16:05 02: 00000053 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 0000045C 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 6 tx 4 rx 13 15:16:05 0A: 00000004 15:16:05 02: 00000064 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 0000046D 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 7 tx 4 rx 12 15:16:05 0A: 00000004 15:16:05 02: 00000074 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 0000047C 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 8 tx 3 rx 11 15:16:05 0A: 00000004 15:16:05 02: 00000083 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 0000048B 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 9 tx 3 rx 10 15:16:05 0A: 00000004 15:16:05 02: 00000093 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 0000049A 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 10 tx 4 rx 11 15:16:05 0A: 00000004 15:16:05 02: 000000A4 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 000004AB 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 11 tx 4 rx 10 15:16:05 0A: 00000004 15:16:05 02: 000000B4 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 000004BA 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 12 tx 5 rx 11 15:16:05 0A: 00000004 15:16:05 02: 000000C5 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 000004CB 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 13 tx 5 rx 10 15:16:05 0A: 00000004 15:16:05 02: 000000D5 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 000004DA 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 14 tx 6 rx 11 15:16:05 0A: 00000004 15:16:05 02: 000000E6 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 000004EB 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 15 tx 6 rx 10 15:16:05 0A: 00000004 15:16:05 02: 000000F6 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 000004FA 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 16 tx 5 rx 9 15:16:05 0A: 00000004 15:16:05 02: 00000105 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 00000509 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 17 tx 5 rx 8 15:16:05 0A: 00000004 15:16:05 02: 00000115 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 00000518 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 18 tx 6 rx 9 15:16:05 0A: 00000004 15:16:05 02: 00000126 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 00000529 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 19 tx 6 rx 8 15:16:05 0A: 00000004 15:16:05 02: 00000136 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 00000538 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 20 tx 7 rx 9 15:16:05 0A: 00000004 15:16:05 02: 00000147 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 00000549 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 21 tx 7 rx 8 15:16:05 0A: 00000004 15:16:05 02: 00000157 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 00000558 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 22 tx 8 rx 9 15:16:05 0A: 00000004 15:16:05 02: 00000168 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 00000569 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 23 tx 8 rx 8 15:16:05 0A: 00000004 15:16:05 02: 00000178 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 00000578 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 24 tx 7 rx 7 15:16:05 0A: 00000004 15:16:05 02: 00000187 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 00000587 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 25 tx 7 rx 6 15:16:05 0A: 00000004 15:16:05 02: 00000197 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 00000596 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 26 tx 8 rx 7 15:16:05 0A: 00000004 15:16:05 02: 000001A8 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 000005A7 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 27 tx 8 rx 6 15:16:05 0A: 00000004 15:16:05 02: 000001B8 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 000005B6 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 28 tx 9 rx 7 15:16:05 0A: 00000004 15:16:05 02: 000001C9 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 000005C7 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 29 tx 9 rx 6 15:16:05 0A: 00000004 15:16:05 02: 000001D9 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 000005D6 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 30 tx 10 rx 7 15:16:05 0A: 00000004 15:16:05 02: 000001EA 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 000005E7 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 31 tx 10 rx 6 15:16:05 0A: 00000004 15:16:05 02: 000001FA 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 000005F6 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 32 tx 9 rx 5 15:16:05 0A: 00000004 15:16:05 02: 00000209 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 00000605 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 33 tx 9 rx 4 15:16:05 0A: 00000004 15:16:05 02: 00000219 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 00000614 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 34 tx 10 rx 5 15:16:05 0A: 00000004 15:16:05 02: 0000022A 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 00000625 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 35 tx 10 rx 4 15:16:05 0A: 00000004 15:16:05 02: 0000023A 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 00000634 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 36 tx 11 rx 5 15:16:05 0A: 00000004 15:16:05 02: 0000024B 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 00000645 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 37 tx 11 rx 4 15:16:05 0A: 00000004 15:16:05 02: 0000025B 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 00000654 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 38 tx 12 rx 5 15:16:05 0A: 00000004 15:16:05 02: 0000026C 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 00000665 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 39 tx 12 rx 4 15:16:05 0A: 00000004 15:16:05 02: 0000027C 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 00000674 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 40 tx 11 rx 3 15:16:05 0A: 00000004 15:16:05 02: 0000028B 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 00000683 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 41 tx 11 rx 2 15:16:05 0A: 00000004 15:16:05 02: 0000029B 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 00000692 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 42 tx 12 rx 3 15:16:05 0A: 00000004 15:16:05 02: 000002AC 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 000006A3 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 43 tx 12 rx 2 15:16:05 0A: 00000004 15:16:05 02: 000002BC 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 000006B2 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 44 tx 13 rx 3 15:16:05 0A: 00000004 15:16:05 02: 000002CD 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 000006C3 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 45 tx 13 rx 2 15:16:05 0A: 00000004 15:16:05 02: 000002DD 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 000006D2 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 46 tx 14 rx 3 15:16:05 0A: 00000004 15:16:05 02: 000002EE 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 000006E3 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 47 tx 14 rx 2 15:16:05 0A: 00000004 15:16:05 02: 000002FE 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 000006F2 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 48 tx 0 rx 15 15:16:05 0A: 00000004 15:16:05 02: 00000300 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 0000070F 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // ram write 3 sw 49 tx 15 rx 0 15:16:05 0A: 00000004 15:16:05 02: 0000031F 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 0A: 00000004 15:16:05 02: 00000710 15:16:05 02: 00009000 15:16:05 0A: 00000004 15:16:05 15:16:05 // reset seq 15:16:05 08: 00000001 15:16:05 08: 00031000 15:16:05 0E: 00000001 15:16:05 0E: 00000000 15:16:05 15:16:05 // start 15:16:05 0E: 0000000C 15:16:05 0C: 00000001 15:16:21 15:16:21 // reset mcu 15:16:21 16: 023C3460 15:16:21 17: 00000001 15:16:21 15:16:21 // encoder limit 100 15:16:21 11: 00000064 15:16:21 15:16:21 // encoder virt rate 136691 15:16:21 10: 000215F3 15:16:21 15:16:21 // trx mask 00100000 15:16:21 0A: 00000004 15:16:21 15:16:21 // sched write 0 adc_sample_time freq 62 15:16:21 08: 0000003E 15:16:21 08: 00025000 15:16:21 15:16:21 // sched write 0 adc_sample_time sw 62 15:16:21 08: 0000003E 15:16:21 08: 00029000 15:16:21 15:16:21 // sched write 0 timeout freq 4250 15:16:21 08: 0000109A 15:16:21 08: 0000D000 15:16:21 15:16:21 // sched write 0 timeout freqmaxtomin 11250 15:16:21 08: 00002BF2 15:16:21 08: 00035000 15:16:21 15:16:21 // sched write 0 timeout sw 324 15:16:21 08: 00000144 15:16:21 08: 00011000 15:16:21 15:16:21 // pll write 0 tx 2 2 lo 2 2 15:16:21 08: 02000002 15:16:21 08: 00015000 15:16:21 08: 12000002 15:16:21 08: 00015000 15:16:21 15:16:21 // pll write 0 tx 3 70 lo 3 70 15:16:21 08: 03000046 15:16:21 08: 00015000 15:16:21 08: 13000046 15:16:21 08: 00015000 15:16:21 15:16:21 // pll write 0 tx 4 0 lo 4 2090000 15:16:21 08: 04000000 15:16:21 08: 00015000 15:16:21 08: 141FE410 15:16:21 08: 00015000 15:16:21 15:16:21 // pll write 0 tx 5 0 lo 5 0 15:16:21 08: 05000000 15:16:21 08: 00015000 15:16:21 08: 15000000 15:16:21 08: 00015000 15:16:21 15:16:21 // pll write 0 tx 6 265863 lo 6 265863 15:16:21 08: 06040E87 15:16:21 08: 00015000 15:16:21 08: 16040E87 15:16:21 08: 00015000 15:16:21 15:16:21 // pll write 0 tx 7 1049850 lo 7 1049850 15:16:21 08: 071004FA 15:16:21 08: 00015000 15:16:21 08: 171004FA 15:16:21 08: 00015000 15:16:21 15:16:21 // pll write 0 tx 8 12799 lo 8 12799 15:16:21 08: 080031FF 15:16:21 08: 00015000 15:16:21 08: 180031FF 15:16:21 08: 00015000 15:16:21 15:16:21 // pll write 0 tx 9 2359308 lo 9 2359308 15:16:21 08: 0924000C 15:16:21 08: 00015000 15:16:21 08: 1924000C 15:16:21 08: 00015000 15:16:21 15:16:21 // pll write 0 tx 10 0 lo 10 0 15:16:21 08: 0A000000 15:16:21 08: 00015000 15:16:21 08: 1A000000 15:16:21 08: 00015000 15:16:21 15:16:21 // pll write 0 tx 11 2168 lo 11 2168 15:16:21 08: 0B000878 15:16:21 08: 00015000 15:16:21 08: 1B000878 15:16:21 08: 00015000 15:16:21 15:16:21 // pll write 0 tx 13 1 lo 13 1 15:16:21 08: 0D000001 15:16:21 08: 00015000 15:16:21 08: 1D000001 15:16:21 08: 00015000 15:16:21 15:16:21 // freq write 0 limit 101 15:16:21 08: 00000065 15:16:21 08: 00021000 15:16:21 15:16:21 // freq write 0 vectors_total 1 15:16:21 08: 00000001 15:16:21 08: 0002D000 15:16:21 15:16:21 // freq write 3 span 0 [13500:50:18500] [13525:50:18525] MHz 15:16:21 0A: 00000004 15:16:21 02: 24A9A700 15:16:21 02: 00001003 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 02FAF080 15:16:21 02: 00001008 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 4EAF9900 15:16:21 02: 00001014 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 26271F40 15:16:21 02: 00001803 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 02FAF080 15:16:21 02: 00001808 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 502D1140 15:16:21 02: 00001814 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 vga 0 rx 36 lo 36 15:16:21 0A: 00000004 15:16:21 02: 00000024 15:16:21 02: 00005000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 00200024 15:16:21 02: 00005000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 0 tx 1 rx 13 15:16:21 0A: 00000004 15:16:21 02: 00000001 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 0000040D 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 1 tx 1 rx 12 15:16:21 0A: 00000004 15:16:21 02: 00000011 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 0000041C 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 2 tx 2 rx 13 15:16:21 0A: 00000004 15:16:21 02: 00000022 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 0000042D 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 3 tx 2 rx 12 15:16:21 0A: 00000004 15:16:21 02: 00000032 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 0000043C 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 4 tx 3 rx 13 15:16:21 0A: 00000004 15:16:21 02: 00000043 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 0000044D 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 5 tx 3 rx 12 15:16:21 0A: 00000004 15:16:21 02: 00000053 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 0000045C 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 6 tx 4 rx 13 15:16:21 0A: 00000004 15:16:21 02: 00000064 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 0000046D 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 7 tx 4 rx 12 15:16:21 0A: 00000004 15:16:21 02: 00000074 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 0000047C 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 8 tx 3 rx 11 15:16:21 0A: 00000004 15:16:21 02: 00000083 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 0000048B 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 9 tx 3 rx 10 15:16:21 0A: 00000004 15:16:21 02: 00000093 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 0000049A 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 10 tx 4 rx 11 15:16:21 0A: 00000004 15:16:21 02: 000000A4 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 000004AB 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 11 tx 4 rx 10 15:16:21 0A: 00000004 15:16:21 02: 000000B4 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 000004BA 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 12 tx 5 rx 11 15:16:21 0A: 00000004 15:16:21 02: 000000C5 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 000004CB 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 13 tx 5 rx 10 15:16:21 0A: 00000004 15:16:21 02: 000000D5 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 000004DA 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 14 tx 6 rx 11 15:16:21 0A: 00000004 15:16:21 02: 000000E6 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 000004EB 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 15 tx 6 rx 10 15:16:21 0A: 00000004 15:16:21 02: 000000F6 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 000004FA 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 16 tx 5 rx 9 15:16:21 0A: 00000004 15:16:21 02: 00000105 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 00000509 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 17 tx 5 rx 8 15:16:21 0A: 00000004 15:16:21 02: 00000115 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 00000518 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 18 tx 6 rx 9 15:16:21 0A: 00000004 15:16:21 02: 00000126 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 00000529 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 19 tx 6 rx 8 15:16:21 0A: 00000004 15:16:21 02: 00000136 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 00000538 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 20 tx 7 rx 9 15:16:21 0A: 00000004 15:16:21 02: 00000147 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 00000549 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 21 tx 7 rx 8 15:16:21 0A: 00000004 15:16:21 02: 00000157 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 00000558 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 22 tx 8 rx 9 15:16:21 0A: 00000004 15:16:21 02: 00000168 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 00000569 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 23 tx 8 rx 8 15:16:21 0A: 00000004 15:16:21 02: 00000178 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 00000578 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 24 tx 7 rx 7 15:16:21 0A: 00000004 15:16:21 02: 00000187 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 00000587 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 25 tx 7 rx 6 15:16:21 0A: 00000004 15:16:21 02: 00000197 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 00000596 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 26 tx 8 rx 7 15:16:21 0A: 00000004 15:16:21 02: 000001A8 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 000005A7 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 27 tx 8 rx 6 15:16:21 0A: 00000004 15:16:21 02: 000001B8 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 000005B6 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 28 tx 9 rx 7 15:16:21 0A: 00000004 15:16:21 02: 000001C9 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 000005C7 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 29 tx 9 rx 6 15:16:21 0A: 00000004 15:16:21 02: 000001D9 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 000005D6 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 30 tx 10 rx 7 15:16:21 0A: 00000004 15:16:21 02: 000001EA 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 000005E7 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 31 tx 10 rx 6 15:16:21 0A: 00000004 15:16:21 02: 000001FA 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 000005F6 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 32 tx 9 rx 5 15:16:21 0A: 00000004 15:16:21 02: 00000209 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 00000605 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 33 tx 9 rx 4 15:16:21 0A: 00000004 15:16:21 02: 00000219 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 00000614 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 34 tx 10 rx 5 15:16:21 0A: 00000004 15:16:21 02: 0000022A 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 00000625 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 35 tx 10 rx 4 15:16:21 0A: 00000004 15:16:21 02: 0000023A 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 00000634 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 36 tx 11 rx 5 15:16:21 0A: 00000004 15:16:21 02: 0000024B 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 00000645 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 37 tx 11 rx 4 15:16:21 0A: 00000004 15:16:21 02: 0000025B 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 00000654 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 38 tx 12 rx 5 15:16:21 0A: 00000004 15:16:21 02: 0000026C 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 00000665 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 39 tx 12 rx 4 15:16:21 0A: 00000004 15:16:21 02: 0000027C 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 00000674 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 40 tx 11 rx 3 15:16:21 0A: 00000004 15:16:21 02: 0000028B 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 00000683 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 41 tx 11 rx 2 15:16:21 0A: 00000004 15:16:21 02: 0000029B 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 00000692 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 42 tx 12 rx 3 15:16:21 0A: 00000004 15:16:21 02: 000002AC 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 000006A3 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 43 tx 12 rx 2 15:16:21 0A: 00000004 15:16:21 02: 000002BC 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 000006B2 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 44 tx 13 rx 3 15:16:21 0A: 00000004 15:16:21 02: 000002CD 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 000006C3 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 45 tx 13 rx 2 15:16:21 0A: 00000004 15:16:21 02: 000002DD 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 000006D2 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 46 tx 14 rx 3 15:16:21 0A: 00000004 15:16:21 02: 000002EE 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 000006E3 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 47 tx 14 rx 2 15:16:21 0A: 00000004 15:16:21 02: 000002FE 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 000006F2 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 48 tx 0 rx 15 15:16:21 0A: 00000004 15:16:21 02: 00000300 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 0000070F 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // ram write 3 sw 49 tx 15 rx 0 15:16:21 0A: 00000004 15:16:21 02: 0000031F 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 0A: 00000004 15:16:21 02: 00000710 15:16:21 02: 00009000 15:16:21 0A: 00000004 15:16:21 15:16:21 // reset seq 15:16:21 08: 00000001 15:16:21 08: 00031000 15:16:21 0E: 00000001 15:16:21 0E: 00000000 15:16:21 15:16:21 // start 15:16:21 0E: 0000000C 15:16:21 0C: 00000001 15:16:21 15:16:21 // stop now 15:16:21 0E: 00000004 15:16:49 15:16:49 // chmod 3 cnt 15:16:49 0A: 00000004 15:16:49 02: 00000001 15:16:49 02: 00039100 15:16:49 0A: 000000FF 15:16:50 15:16:50 // chmod 3 cnt 15:16:50 0A: 00000004 15:16:50 02: 00000001 15:16:50 02: 00039100 15:16:50 0A: 000000FF 15:16:50 15:16:50 // chmod 3 cnt 15:16:50 0A: 00000004 15:16:50 02: 00000001 15:16:50 02: 00039100 15:16:50 0A: 000000FF 15:16:50 15:16:50 // chmod 3 cnt 15:16:50 0A: 00000004 15:16:50 02: 00000001 15:16:50 02: 00039100 15:16:50 0A: 000000FF 15:16:50 15:16:50 // chmod 3 cnt 15:16:50 0A: 00000004 15:16:50 02: 00000001 15:16:50 02: 00039100 15:16:50 0A: 000000FF 15:16:50 15:16:50 // chmod 3 cnt 15:16:50 0A: 00000004 15:16:50 02: 00000001 15:16:50 02: 00039100 15:16:50 0A: 000000FF 15:16:50 15:16:50 // chmod 3 cnt 15:16:50 0A: 00000004 15:16:50 02: 00000001 15:16:50 02: 00039100 15:16:50 0A: 000000FF 15:16:50 15:16:50 // chmod 3 cnt 15:16:50 0A: 00000004 15:16:50 02: 00000001 15:16:50 02: 00039100 15:16:50 0A: 000000FF 15:16:52 15:16:52 // reset mcu 15:16:52 16: 023C3460 15:16:52 17: 00000001 15:16:52 15:16:52 // encoder limit 100 15:16:52 11: 00000064 15:16:52 15:16:52 // encoder virt rate 136691 15:16:52 10: 000215F3 15:16:52 15:16:52 // trx mask 00100000 15:16:52 0A: 00000004 15:16:52 15:16:52 // sched write 0 adc_sample_time freq 62 15:16:52 08: 0000003E 15:16:52 08: 00025000 15:16:52 15:16:52 // sched write 0 adc_sample_time sw 62 15:16:52 08: 0000003E 15:16:52 08: 00029000 15:16:52 15:16:52 // sched write 0 timeout freq 4250 15:16:52 08: 0000109A 15:16:52 08: 0000D000 15:16:52 15:16:52 // sched write 0 timeout freqmaxtomin 11250 15:16:52 08: 00002BF2 15:16:52 08: 00035000 15:16:52 15:16:52 // sched write 0 timeout sw 324 15:16:52 08: 00000144 15:16:52 08: 00011000 15:16:52 15:16:52 // pll write 0 tx 2 2 lo 2 2 15:16:52 08: 02000002 15:16:52 08: 00015000 15:16:52 08: 12000002 15:16:52 08: 00015000 15:16:52 15:16:52 // pll write 0 tx 3 70 lo 3 70 15:16:52 08: 03000046 15:16:52 08: 00015000 15:16:52 08: 13000046 15:16:52 08: 00015000 15:16:52 15:16:52 // pll write 0 tx 4 0 lo 4 2090000 15:16:52 08: 04000000 15:16:52 08: 00015000 15:16:52 08: 141FE410 15:16:52 08: 00015000 15:16:52 15:16:52 // pll write 0 tx 5 0 lo 5 0 15:16:52 08: 05000000 15:16:52 08: 00015000 15:16:52 08: 15000000 15:16:52 08: 00015000 15:16:52 15:16:52 // pll write 0 tx 6 265863 lo 6 265863 15:16:52 08: 06040E87 15:16:52 08: 00015000 15:16:52 08: 16040E87 15:16:52 08: 00015000 15:16:52 15:16:52 // pll write 0 tx 7 1049850 lo 7 1049850 15:16:52 08: 071004FA 15:16:52 08: 00015000 15:16:52 08: 171004FA 15:16:52 08: 00015000 15:16:52 15:16:52 // pll write 0 tx 8 12799 lo 8 12799 15:16:52 08: 080031FF 15:16:52 08: 00015000 15:16:52 08: 180031FF 15:16:52 08: 00015000 15:16:52 15:16:52 // pll write 0 tx 9 2359308 lo 9 2359308 15:16:52 08: 0924000C 15:16:52 08: 00015000 15:16:52 08: 1924000C 15:16:52 08: 00015000 15:16:52 15:16:52 // pll write 0 tx 10 0 lo 10 0 15:16:52 08: 0A000000 15:16:52 08: 00015000 15:16:52 08: 1A000000 15:16:52 08: 00015000 15:16:52 15:16:52 // pll write 0 tx 11 2168 lo 11 2168 15:16:52 08: 0B000878 15:16:52 08: 00015000 15:16:52 08: 1B000878 15:16:52 08: 00015000 15:16:52 15:16:52 // pll write 0 tx 13 1 lo 13 1 15:16:52 08: 0D000001 15:16:52 08: 00015000 15:16:52 08: 1D000001 15:16:52 08: 00015000 15:16:52 15:16:52 // freq write 0 limit 101 15:16:52 08: 00000065 15:16:52 08: 00021000 15:16:52 15:16:52 // freq write 0 vectors_total 1 15:16:52 08: 00000001 15:16:52 08: 0002D000 15:16:52 15:16:52 // freq write 3 span 0 [13500:50:18500] [13525:50:18525] MHz 15:16:52 0A: 00000004 15:16:52 02: 24A9A700 15:16:52 02: 00001003 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 02FAF080 15:16:52 02: 00001008 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 4EAF9900 15:16:52 02: 00001014 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 26271F40 15:16:52 02: 00001803 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 02FAF080 15:16:52 02: 00001808 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 502D1140 15:16:52 02: 00001814 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 vga 0 rx 36 lo 36 15:16:52 0A: 00000004 15:16:52 02: 00000024 15:16:52 02: 00005000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 00200024 15:16:52 02: 00005000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 0 tx 1 rx 13 15:16:52 0A: 00000004 15:16:52 02: 00000001 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 0000040D 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 1 tx 1 rx 12 15:16:52 0A: 00000004 15:16:52 02: 00000011 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 0000041C 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 2 tx 2 rx 13 15:16:52 0A: 00000004 15:16:52 02: 00000022 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 0000042D 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 3 tx 2 rx 12 15:16:52 0A: 00000004 15:16:52 02: 00000032 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 0000043C 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 4 tx 3 rx 13 15:16:52 0A: 00000004 15:16:52 02: 00000043 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 0000044D 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 5 tx 3 rx 12 15:16:52 0A: 00000004 15:16:52 02: 00000053 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 0000045C 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 6 tx 4 rx 13 15:16:52 0A: 00000004 15:16:52 02: 00000064 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 0000046D 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 7 tx 4 rx 12 15:16:52 0A: 00000004 15:16:52 02: 00000074 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 0000047C 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 8 tx 3 rx 11 15:16:52 0A: 00000004 15:16:52 02: 00000083 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 0000048B 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 9 tx 3 rx 10 15:16:52 0A: 00000004 15:16:52 02: 00000093 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 0000049A 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 10 tx 4 rx 11 15:16:52 0A: 00000004 15:16:52 02: 000000A4 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 000004AB 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 11 tx 4 rx 10 15:16:52 0A: 00000004 15:16:52 02: 000000B4 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 000004BA 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 12 tx 5 rx 11 15:16:52 0A: 00000004 15:16:52 02: 000000C5 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 000004CB 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 13 tx 5 rx 10 15:16:52 0A: 00000004 15:16:52 02: 000000D5 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 000004DA 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 14 tx 6 rx 11 15:16:52 0A: 00000004 15:16:52 02: 000000E6 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 000004EB 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 15 tx 6 rx 10 15:16:52 0A: 00000004 15:16:52 02: 000000F6 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 000004FA 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 16 tx 5 rx 9 15:16:52 0A: 00000004 15:16:52 02: 00000105 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 00000509 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 17 tx 5 rx 8 15:16:52 0A: 00000004 15:16:52 02: 00000115 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 00000518 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 18 tx 6 rx 9 15:16:52 0A: 00000004 15:16:52 02: 00000126 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 00000529 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 19 tx 6 rx 8 15:16:52 0A: 00000004 15:16:52 02: 00000136 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 00000538 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 20 tx 7 rx 9 15:16:52 0A: 00000004 15:16:52 02: 00000147 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 00000549 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 21 tx 7 rx 8 15:16:52 0A: 00000004 15:16:52 02: 00000157 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 00000558 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 22 tx 8 rx 9 15:16:52 0A: 00000004 15:16:52 02: 00000168 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 00000569 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 23 tx 8 rx 8 15:16:52 0A: 00000004 15:16:52 02: 00000178 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 00000578 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 24 tx 7 rx 7 15:16:52 0A: 00000004 15:16:52 02: 00000187 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 00000587 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 25 tx 7 rx 6 15:16:52 0A: 00000004 15:16:52 02: 00000197 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 00000596 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 26 tx 8 rx 7 15:16:52 0A: 00000004 15:16:52 02: 000001A8 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 000005A7 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 27 tx 8 rx 6 15:16:52 0A: 00000004 15:16:52 02: 000001B8 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 000005B6 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 28 tx 9 rx 7 15:16:52 0A: 00000004 15:16:52 02: 000001C9 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 000005C7 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 29 tx 9 rx 6 15:16:52 0A: 00000004 15:16:52 02: 000001D9 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 000005D6 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 30 tx 10 rx 7 15:16:52 0A: 00000004 15:16:52 02: 000001EA 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 000005E7 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 31 tx 10 rx 6 15:16:52 0A: 00000004 15:16:52 02: 000001FA 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 000005F6 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 32 tx 9 rx 5 15:16:52 0A: 00000004 15:16:52 02: 00000209 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 00000605 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 33 tx 9 rx 4 15:16:52 0A: 00000004 15:16:52 02: 00000219 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 00000614 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 34 tx 10 rx 5 15:16:52 0A: 00000004 15:16:52 02: 0000022A 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 00000625 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 35 tx 10 rx 4 15:16:52 0A: 00000004 15:16:52 02: 0000023A 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 00000634 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 36 tx 11 rx 5 15:16:52 0A: 00000004 15:16:52 02: 0000024B 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 00000645 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 37 tx 11 rx 4 15:16:52 0A: 00000004 15:16:52 02: 0000025B 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 00000654 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 38 tx 12 rx 5 15:16:52 0A: 00000004 15:16:52 02: 0000026C 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 00000665 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 39 tx 12 rx 4 15:16:52 0A: 00000004 15:16:52 02: 0000027C 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 00000674 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 40 tx 11 rx 3 15:16:52 0A: 00000004 15:16:52 02: 0000028B 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 00000683 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 41 tx 11 rx 2 15:16:52 0A: 00000004 15:16:52 02: 0000029B 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 00000692 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 42 tx 12 rx 3 15:16:52 0A: 00000004 15:16:52 02: 000002AC 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 000006A3 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 43 tx 12 rx 2 15:16:52 0A: 00000004 15:16:52 02: 000002BC 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 000006B2 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 44 tx 13 rx 3 15:16:52 0A: 00000004 15:16:52 02: 000002CD 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 000006C3 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 45 tx 13 rx 2 15:16:52 0A: 00000004 15:16:52 02: 000002DD 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 000006D2 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 46 tx 14 rx 3 15:16:52 0A: 00000004 15:16:52 02: 000002EE 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 000006E3 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 47 tx 14 rx 2 15:16:52 0A: 00000004 15:16:52 02: 000002FE 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 000006F2 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 48 tx 0 rx 15 15:16:52 0A: 00000004 15:16:52 02: 00000300 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 0000070F 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // ram write 3 sw 49 tx 15 rx 0 15:16:52 0A: 00000004 15:16:52 02: 0000031F 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 0A: 00000004 15:16:52 02: 00000710 15:16:52 02: 00009000 15:16:52 0A: 00000004 15:16:52 15:16:52 // reset seq 15:16:52 08: 00000001 15:16:52 08: 00031000 15:16:52 0E: 00000001 15:16:52 0E: 00000000 15:16:52 15:16:52 // start 15:16:52 0E: 0000000C 15:16:52 0C: 00000001 15:18:59 15:18:59 // reset mcu 15:18:59 16: 023C3460 15:18:59 17: 00000001 15:18:59 15:18:59 // encoder limit 100 15:18:59 11: 00000064 15:18:59 15:18:59 // encoder virt rate 136691 15:18:59 10: 000215F3 15:18:59 15:18:59 // trx mask 00100000 15:18:59 0A: 00000004 15:18:59 15:18:59 // sched write 0 adc_sample_time freq 62 15:18:59 08: 0000003E 15:18:59 08: 00025000 15:18:59 15:18:59 // sched write 0 adc_sample_time sw 62 15:18:59 08: 0000003E 15:18:59 08: 00029000 15:18:59 15:18:59 // sched write 0 timeout freq 4250 15:18:59 08: 0000109A 15:18:59 08: 0000D000 15:18:59 15:18:59 // sched write 0 timeout freqmaxtomin 11250 15:18:59 08: 00002BF2 15:18:59 08: 00035000 15:18:59 15:18:59 // sched write 0 timeout sw 324 15:18:59 08: 00000144 15:18:59 08: 00011000 15:18:59 15:18:59 // pll write 0 tx 2 2 lo 2 2 15:18:59 08: 02000002 15:18:59 08: 00015000 15:18:59 08: 12000002 15:18:59 08: 00015000 15:18:59 15:18:59 // pll write 0 tx 3 70 lo 3 70 15:18:59 08: 03000046 15:18:59 08: 00015000 15:18:59 08: 13000046 15:18:59 08: 00015000 15:18:59 15:18:59 // pll write 0 tx 4 0 lo 4 2090000 15:18:59 08: 04000000 15:18:59 08: 00015000 15:18:59 08: 141FE410 15:18:59 08: 00015000 15:18:59 15:18:59 // pll write 0 tx 5 0 lo 5 0 15:18:59 08: 05000000 15:18:59 08: 00015000 15:18:59 08: 15000000 15:18:59 08: 00015000 15:18:59 15:18:59 // pll write 0 tx 6 265863 lo 6 265863 15:18:59 08: 06040E87 15:18:59 08: 00015000 15:18:59 08: 16040E87 15:18:59 08: 00015000 15:18:59 15:18:59 // pll write 0 tx 7 1049850 lo 7 1049850 15:18:59 08: 071004FA 15:18:59 08: 00015000 15:18:59 08: 171004FA 15:18:59 08: 00015000 15:18:59 15:18:59 // pll write 0 tx 8 12799 lo 8 12799 15:18:59 08: 080031FF 15:18:59 08: 00015000 15:18:59 08: 180031FF 15:18:59 08: 00015000 15:18:59 15:18:59 // pll write 0 tx 9 2359308 lo 9 2359308 15:18:59 08: 0924000C 15:18:59 08: 00015000 15:18:59 08: 1924000C 15:18:59 08: 00015000 15:18:59 15:18:59 // pll write 0 tx 10 0 lo 10 0 15:18:59 08: 0A000000 15:18:59 08: 00015000 15:18:59 08: 1A000000 15:18:59 08: 00015000 15:18:59 15:18:59 // pll write 0 tx 11 2168 lo 11 2168 15:18:59 08: 0B000878 15:18:59 08: 00015000 15:18:59 08: 1B000878 15:18:59 08: 00015000 15:18:59 15:18:59 // pll write 0 tx 13 1 lo 13 1 15:18:59 08: 0D000001 15:18:59 08: 00015000 15:18:59 08: 1D000001 15:18:59 08: 00015000 15:18:59 15:18:59 // freq write 0 limit 101 15:18:59 08: 00000065 15:18:59 08: 00021000 15:18:59 15:18:59 // freq write 0 vectors_total 1 15:18:59 08: 00000001 15:18:59 08: 0002D000 15:18:59 15:18:59 // freq write 3 span 0 [13500:50:18500] [13525:50:18525] MHz 15:18:59 0A: 00000004 15:18:59 02: 24A9A700 15:18:59 02: 00001003 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 02FAF080 15:18:59 02: 00001008 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 4EAF9900 15:18:59 02: 00001014 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 26271F40 15:18:59 02: 00001803 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 02FAF080 15:18:59 02: 00001808 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 502D1140 15:18:59 02: 00001814 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 vga 0 rx 36 lo 36 15:18:59 0A: 00000004 15:18:59 02: 00000024 15:18:59 02: 00005000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 00200024 15:18:59 02: 00005000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 0 tx 1 rx 13 15:18:59 0A: 00000004 15:18:59 02: 00000001 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 0000040D 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 1 tx 1 rx 12 15:18:59 0A: 00000004 15:18:59 02: 00000011 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 0000041C 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 2 tx 2 rx 13 15:18:59 0A: 00000004 15:18:59 02: 00000022 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 0000042D 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 3 tx 2 rx 12 15:18:59 0A: 00000004 15:18:59 02: 00000032 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 0000043C 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 4 tx 3 rx 13 15:18:59 0A: 00000004 15:18:59 02: 00000043 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 0000044D 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 5 tx 3 rx 12 15:18:59 0A: 00000004 15:18:59 02: 00000053 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 0000045C 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 6 tx 4 rx 13 15:18:59 0A: 00000004 15:18:59 02: 00000064 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 0000046D 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 7 tx 4 rx 12 15:18:59 0A: 00000004 15:18:59 02: 00000074 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 0000047C 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 8 tx 3 rx 11 15:18:59 0A: 00000004 15:18:59 02: 00000083 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 0000048B 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 9 tx 3 rx 10 15:18:59 0A: 00000004 15:18:59 02: 00000093 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 0000049A 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 10 tx 4 rx 11 15:18:59 0A: 00000004 15:18:59 02: 000000A4 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 000004AB 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 11 tx 4 rx 10 15:18:59 0A: 00000004 15:18:59 02: 000000B4 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 000004BA 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 12 tx 5 rx 11 15:18:59 0A: 00000004 15:18:59 02: 000000C5 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 000004CB 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 13 tx 5 rx 10 15:18:59 0A: 00000004 15:18:59 02: 000000D5 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 000004DA 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 14 tx 6 rx 11 15:18:59 0A: 00000004 15:18:59 02: 000000E6 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 000004EB 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 15 tx 6 rx 10 15:18:59 0A: 00000004 15:18:59 02: 000000F6 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 000004FA 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 16 tx 5 rx 9 15:18:59 0A: 00000004 15:18:59 02: 00000105 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 00000509 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 17 tx 5 rx 8 15:18:59 0A: 00000004 15:18:59 02: 00000115 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 00000518 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 18 tx 6 rx 9 15:18:59 0A: 00000004 15:18:59 02: 00000126 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 00000529 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 19 tx 6 rx 8 15:18:59 0A: 00000004 15:18:59 02: 00000136 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 00000538 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 20 tx 7 rx 9 15:18:59 0A: 00000004 15:18:59 02: 00000147 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 00000549 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 21 tx 7 rx 8 15:18:59 0A: 00000004 15:18:59 02: 00000157 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 00000558 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 22 tx 8 rx 9 15:18:59 0A: 00000004 15:18:59 02: 00000168 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 00000569 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 23 tx 8 rx 8 15:18:59 0A: 00000004 15:18:59 02: 00000178 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 00000578 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 24 tx 7 rx 7 15:18:59 0A: 00000004 15:18:59 02: 00000187 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 00000587 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 25 tx 7 rx 6 15:18:59 0A: 00000004 15:18:59 02: 00000197 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 00000596 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 26 tx 8 rx 7 15:18:59 0A: 00000004 15:18:59 02: 000001A8 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 000005A7 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 27 tx 8 rx 6 15:18:59 0A: 00000004 15:18:59 02: 000001B8 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 000005B6 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 28 tx 9 rx 7 15:18:59 0A: 00000004 15:18:59 02: 000001C9 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 000005C7 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 29 tx 9 rx 6 15:18:59 0A: 00000004 15:18:59 02: 000001D9 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 000005D6 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 30 tx 10 rx 7 15:18:59 0A: 00000004 15:18:59 02: 000001EA 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 000005E7 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 31 tx 10 rx 6 15:18:59 0A: 00000004 15:18:59 02: 000001FA 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 000005F6 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 32 tx 9 rx 5 15:18:59 0A: 00000004 15:18:59 02: 00000209 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 00000605 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 33 tx 9 rx 4 15:18:59 0A: 00000004 15:18:59 02: 00000219 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 00000614 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 34 tx 10 rx 5 15:18:59 0A: 00000004 15:18:59 02: 0000022A 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 00000625 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 35 tx 10 rx 4 15:18:59 0A: 00000004 15:18:59 02: 0000023A 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 00000634 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 36 tx 11 rx 5 15:18:59 0A: 00000004 15:18:59 02: 0000024B 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 00000645 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 37 tx 11 rx 4 15:18:59 0A: 00000004 15:18:59 02: 0000025B 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 00000654 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 38 tx 12 rx 5 15:18:59 0A: 00000004 15:18:59 02: 0000026C 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 00000665 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 39 tx 12 rx 4 15:18:59 0A: 00000004 15:18:59 02: 0000027C 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 00000674 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 40 tx 11 rx 3 15:18:59 0A: 00000004 15:18:59 02: 0000028B 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 00000683 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 41 tx 11 rx 2 15:18:59 0A: 00000004 15:18:59 02: 0000029B 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 00000692 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 42 tx 12 rx 3 15:18:59 0A: 00000004 15:18:59 02: 000002AC 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 000006A3 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 43 tx 12 rx 2 15:18:59 0A: 00000004 15:18:59 02: 000002BC 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 000006B2 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 44 tx 13 rx 3 15:18:59 0A: 00000004 15:18:59 02: 000002CD 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 000006C3 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 45 tx 13 rx 2 15:18:59 0A: 00000004 15:18:59 02: 000002DD 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 000006D2 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 46 tx 14 rx 3 15:18:59 0A: 00000004 15:18:59 02: 000002EE 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 000006E3 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 47 tx 14 rx 2 15:18:59 0A: 00000004 15:18:59 02: 000002FE 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 000006F2 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 48 tx 0 rx 15 15:18:59 0A: 00000004 15:18:59 02: 00000300 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 0000070F 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // ram write 3 sw 49 tx 15 rx 0 15:18:59 0A: 00000004 15:18:59 02: 0000031F 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 0A: 00000004 15:18:59 02: 00000710 15:18:59 02: 00009000 15:18:59 0A: 00000004 15:18:59 15:18:59 // reset seq 15:18:59 08: 00000001 15:18:59 08: 00031000 15:18:59 0E: 00000001 15:18:59 0E: 00000000 15:18:59 15:18:59 // start 15:18:59 0E: 0000000C 15:18:59 0C: 00000001 15:19:01 15:19:01 // stop now 15:19:01 0E: 00000004 15:19:02 15:19:02 // reset mcu 15:19:02 16: 023C3460 15:19:02 17: 00000001 15:19:02 15:19:02 // encoder limit 100 15:19:02 11: 00000064 15:19:02 15:19:02 // encoder virt rate 136691 15:19:02 10: 000215F3 15:19:02 15:19:02 // trx mask 00100000 15:19:02 0A: 00000004 15:19:02 15:19:02 // sched write 0 adc_sample_time freq 62 15:19:02 08: 0000003E 15:19:02 08: 00025000 15:19:02 15:19:02 // sched write 0 adc_sample_time sw 62 15:19:02 08: 0000003E 15:19:02 08: 00029000 15:19:02 15:19:02 // sched write 0 timeout freq 4250 15:19:02 08: 0000109A 15:19:02 08: 0000D000 15:19:02 15:19:02 // sched write 0 timeout freqmaxtomin 11250 15:19:02 08: 00002BF2 15:19:02 08: 00035000 15:19:02 15:19:02 // sched write 0 timeout sw 324 15:19:02 08: 00000144 15:19:02 08: 00011000 15:19:02 15:19:02 // pll write 0 tx 2 2 lo 2 2 15:19:02 08: 02000002 15:19:02 08: 00015000 15:19:02 08: 12000002 15:19:02 08: 00015000 15:19:02 15:19:02 // pll write 0 tx 3 70 lo 3 70 15:19:02 08: 03000046 15:19:02 08: 00015000 15:19:02 08: 13000046 15:19:02 08: 00015000 15:19:02 15:19:02 // pll write 0 tx 4 0 lo 4 2090000 15:19:02 08: 04000000 15:19:02 08: 00015000 15:19:02 08: 141FE410 15:19:02 08: 00015000 15:19:02 15:19:02 // pll write 0 tx 5 0 lo 5 0 15:19:02 08: 05000000 15:19:02 08: 00015000 15:19:02 08: 15000000 15:19:02 08: 00015000 15:19:02 15:19:02 // pll write 0 tx 6 265863 lo 6 265863 15:19:02 08: 06040E87 15:19:02 08: 00015000 15:19:02 08: 16040E87 15:19:02 08: 00015000 15:19:02 15:19:02 // pll write 0 tx 7 1049850 lo 7 1049850 15:19:02 08: 071004FA 15:19:02 08: 00015000 15:19:02 08: 171004FA 15:19:02 08: 00015000 15:19:02 15:19:02 // pll write 0 tx 8 12799 lo 8 12799 15:19:02 08: 080031FF 15:19:02 08: 00015000 15:19:02 08: 180031FF 15:19:02 08: 00015000 15:19:02 15:19:02 // pll write 0 tx 9 2359308 lo 9 2359308 15:19:02 08: 0924000C 15:19:02 08: 00015000 15:19:02 08: 1924000C 15:19:02 08: 00015000 15:19:02 15:19:02 // pll write 0 tx 10 0 lo 10 0 15:19:02 08: 0A000000 15:19:02 08: 00015000 15:19:02 08: 1A000000 15:19:02 08: 00015000 15:19:02 15:19:02 // pll write 0 tx 11 2168 lo 11 2168 15:19:02 08: 0B000878 15:19:02 08: 00015000 15:19:02 08: 1B000878 15:19:02 08: 00015000 15:19:02 15:19:02 // pll write 0 tx 13 1 lo 13 1 15:19:02 08: 0D000001 15:19:02 08: 00015000 15:19:02 08: 1D000001 15:19:02 08: 00015000 15:19:02 15:19:02 // freq write 0 limit 101 15:19:02 08: 00000065 15:19:02 08: 00021000 15:19:02 15:19:02 // freq write 0 vectors_total 1 15:19:02 08: 00000001 15:19:02 08: 0002D000 15:19:02 15:19:02 // freq write 3 span 0 [13500:50:18500] [13525:50:18525] MHz 15:19:02 0A: 00000004 15:19:02 02: 24A9A700 15:19:02 02: 00001003 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 02FAF080 15:19:02 02: 00001008 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 4EAF9900 15:19:02 02: 00001014 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 26271F40 15:19:02 02: 00001803 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 02FAF080 15:19:02 02: 00001808 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 502D1140 15:19:02 02: 00001814 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 vga 0 rx 36 lo 36 15:19:02 0A: 00000004 15:19:02 02: 00000024 15:19:02 02: 00005000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 00200024 15:19:02 02: 00005000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 0 tx 1 rx 13 15:19:02 0A: 00000004 15:19:02 02: 00000001 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 0000040D 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 1 tx 1 rx 12 15:19:02 0A: 00000004 15:19:02 02: 00000011 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 0000041C 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 2 tx 2 rx 13 15:19:02 0A: 00000004 15:19:02 02: 00000022 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 0000042D 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 3 tx 2 rx 12 15:19:02 0A: 00000004 15:19:02 02: 00000032 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 0000043C 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 4 tx 3 rx 13 15:19:02 0A: 00000004 15:19:02 02: 00000043 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 0000044D 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 5 tx 3 rx 12 15:19:02 0A: 00000004 15:19:02 02: 00000053 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 0000045C 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 6 tx 4 rx 13 15:19:02 0A: 00000004 15:19:02 02: 00000064 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 0000046D 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 7 tx 4 rx 12 15:19:02 0A: 00000004 15:19:02 02: 00000074 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 0000047C 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 8 tx 3 rx 11 15:19:02 0A: 00000004 15:19:02 02: 00000083 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 0000048B 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 9 tx 3 rx 10 15:19:02 0A: 00000004 15:19:02 02: 00000093 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 0000049A 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 10 tx 4 rx 11 15:19:02 0A: 00000004 15:19:02 02: 000000A4 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 000004AB 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 11 tx 4 rx 10 15:19:02 0A: 00000004 15:19:02 02: 000000B4 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 000004BA 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 12 tx 5 rx 11 15:19:02 0A: 00000004 15:19:02 02: 000000C5 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 000004CB 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 13 tx 5 rx 10 15:19:02 0A: 00000004 15:19:02 02: 000000D5 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 000004DA 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 14 tx 6 rx 11 15:19:02 0A: 00000004 15:19:02 02: 000000E6 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 000004EB 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 15 tx 6 rx 10 15:19:02 0A: 00000004 15:19:02 02: 000000F6 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 000004FA 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 16 tx 5 rx 9 15:19:02 0A: 00000004 15:19:02 02: 00000105 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 00000509 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 17 tx 5 rx 8 15:19:02 0A: 00000004 15:19:02 02: 00000115 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 00000518 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 18 tx 6 rx 9 15:19:02 0A: 00000004 15:19:02 02: 00000126 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 00000529 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 19 tx 6 rx 8 15:19:02 0A: 00000004 15:19:02 02: 00000136 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 00000538 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 20 tx 7 rx 9 15:19:02 0A: 00000004 15:19:02 02: 00000147 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 00000549 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 21 tx 7 rx 8 15:19:02 0A: 00000004 15:19:02 02: 00000157 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 00000558 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 22 tx 8 rx 9 15:19:02 0A: 00000004 15:19:02 02: 00000168 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 00000569 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 23 tx 8 rx 8 15:19:02 0A: 00000004 15:19:02 02: 00000178 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 00000578 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 24 tx 7 rx 7 15:19:02 0A: 00000004 15:19:02 02: 00000187 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 00000587 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 25 tx 7 rx 6 15:19:02 0A: 00000004 15:19:02 02: 00000197 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 00000596 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 26 tx 8 rx 7 15:19:02 0A: 00000004 15:19:02 02: 000001A8 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 000005A7 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 27 tx 8 rx 6 15:19:02 0A: 00000004 15:19:02 02: 000001B8 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 000005B6 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 28 tx 9 rx 7 15:19:02 0A: 00000004 15:19:02 02: 000001C9 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 000005C7 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 29 tx 9 rx 6 15:19:02 0A: 00000004 15:19:02 02: 000001D9 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 000005D6 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 30 tx 10 rx 7 15:19:02 0A: 00000004 15:19:02 02: 000001EA 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 000005E7 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 31 tx 10 rx 6 15:19:02 0A: 00000004 15:19:02 02: 000001FA 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 000005F6 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 32 tx 9 rx 5 15:19:02 0A: 00000004 15:19:02 02: 00000209 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 00000605 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 33 tx 9 rx 4 15:19:02 0A: 00000004 15:19:02 02: 00000219 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 00000614 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 34 tx 10 rx 5 15:19:02 0A: 00000004 15:19:02 02: 0000022A 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 00000625 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 35 tx 10 rx 4 15:19:02 0A: 00000004 15:19:02 02: 0000023A 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 00000634 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 36 tx 11 rx 5 15:19:02 0A: 00000004 15:19:02 02: 0000024B 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 00000645 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 37 tx 11 rx 4 15:19:02 0A: 00000004 15:19:02 02: 0000025B 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 00000654 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 38 tx 12 rx 5 15:19:02 0A: 00000004 15:19:02 02: 0000026C 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 00000665 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 39 tx 12 rx 4 15:19:02 0A: 00000004 15:19:02 02: 0000027C 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 00000674 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 40 tx 11 rx 3 15:19:02 0A: 00000004 15:19:02 02: 0000028B 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 00000683 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 41 tx 11 rx 2 15:19:02 0A: 00000004 15:19:02 02: 0000029B 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 00000692 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 42 tx 12 rx 3 15:19:02 0A: 00000004 15:19:02 02: 000002AC 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 000006A3 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 43 tx 12 rx 2 15:19:02 0A: 00000004 15:19:02 02: 000002BC 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 000006B2 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 44 tx 13 rx 3 15:19:02 0A: 00000004 15:19:02 02: 000002CD 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 000006C3 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 45 tx 13 rx 2 15:19:02 0A: 00000004 15:19:02 02: 000002DD 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 000006D2 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 46 tx 14 rx 3 15:19:02 0A: 00000004 15:19:02 02: 000002EE 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 000006E3 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 47 tx 14 rx 2 15:19:02 0A: 00000004 15:19:02 02: 000002FE 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 000006F2 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 48 tx 0 rx 15 15:19:02 0A: 00000004 15:19:02 02: 00000300 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 0000070F 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // ram write 3 sw 49 tx 15 rx 0 15:19:02 0A: 00000004 15:19:02 02: 0000031F 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 0A: 00000004 15:19:02 02: 00000710 15:19:02 02: 00009000 15:19:02 0A: 00000004 15:19:02 15:19:02 // reset seq 15:19:02 08: 00000001 15:19:02 08: 00031000 15:19:02 0E: 00000001 15:19:02 0E: 00000000 15:19:02 15:19:02 // start 15:19:02 0E: 0000000C 15:19:02 0C: 00000001 15:19:07 15:19:07 // reset mcu 15:19:07 16: 023C3460 15:19:07 17: 00000001 15:19:07 15:19:07 // encoder limit 100 15:19:07 11: 00000064 15:19:07 15:19:07 // encoder virt rate 136691 15:19:07 10: 000215F3 15:19:07 15:19:07 // trx mask 00100000 15:19:07 0A: 00000004 15:19:07 15:19:07 // sched write 0 adc_sample_time freq 62 15:19:07 08: 0000003E 15:19:07 08: 00025000 15:19:07 15:19:07 // sched write 0 adc_sample_time sw 62 15:19:07 08: 0000003E 15:19:07 08: 00029000 15:19:07 15:19:07 // sched write 0 timeout freq 4250 15:19:07 08: 0000109A 15:19:07 08: 0000D000 15:19:07 15:19:07 // sched write 0 timeout freqmaxtomin 11250 15:19:07 08: 00002BF2 15:19:07 08: 00035000 15:19:07 15:19:07 // sched write 0 timeout sw 324 15:19:07 08: 00000144 15:19:07 08: 00011000 15:19:07 15:19:07 // pll write 0 tx 2 2 lo 2 2 15:19:07 08: 02000002 15:19:07 08: 00015000 15:19:07 08: 12000002 15:19:07 08: 00015000 15:19:07 15:19:07 // pll write 0 tx 3 70 lo 3 70 15:19:07 08: 03000046 15:19:07 08: 00015000 15:19:07 08: 13000046 15:19:07 08: 00015000 15:19:07 15:19:07 // pll write 0 tx 4 0 lo 4 2090000 15:19:07 08: 04000000 15:19:07 08: 00015000 15:19:07 08: 141FE410 15:19:07 08: 00015000 15:19:07 15:19:07 // pll write 0 tx 5 0 lo 5 0 15:19:07 08: 05000000 15:19:07 08: 00015000 15:19:07 08: 15000000 15:19:07 08: 00015000 15:19:07 15:19:07 // pll write 0 tx 6 265863 lo 6 265863 15:19:07 08: 06040E87 15:19:07 08: 00015000 15:19:07 08: 16040E87 15:19:07 08: 00015000 15:19:07 15:19:07 // pll write 0 tx 7 1049850 lo 7 1049850 15:19:07 08: 071004FA 15:19:07 08: 00015000 15:19:07 08: 171004FA 15:19:07 08: 00015000 15:19:07 15:19:07 // pll write 0 tx 8 12799 lo 8 12799 15:19:07 08: 080031FF 15:19:07 08: 00015000 15:19:07 08: 180031FF 15:19:07 08: 00015000 15:19:07 15:19:07 // pll write 0 tx 9 2359308 lo 9 2359308 15:19:07 08: 0924000C 15:19:07 08: 00015000 15:19:07 08: 1924000C 15:19:07 08: 00015000 15:19:07 15:19:07 // pll write 0 tx 10 0 lo 10 0 15:19:07 08: 0A000000 15:19:07 08: 00015000 15:19:07 08: 1A000000 15:19:07 08: 00015000 15:19:07 15:19:07 // pll write 0 tx 11 2168 lo 11 2168 15:19:07 08: 0B000878 15:19:07 08: 00015000 15:19:07 08: 1B000878 15:19:07 08: 00015000 15:19:07 15:19:07 // pll write 0 tx 13 1 lo 13 1 15:19:07 08: 0D000001 15:19:07 08: 00015000 15:19:07 08: 1D000001 15:19:07 08: 00015000 15:19:07 15:19:07 // freq write 0 limit 101 15:19:07 08: 00000065 15:19:07 08: 00021000 15:19:07 15:19:07 // freq write 0 vectors_total 1 15:19:07 08: 00000001 15:19:07 08: 0002D000 15:19:07 15:19:07 // freq write 3 span 0 [13500:50:18500] [13525:50:18525] MHz 15:19:07 0A: 00000004 15:19:07 02: 24A9A700 15:19:07 02: 00001003 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 02FAF080 15:19:07 02: 00001008 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 4EAF9900 15:19:07 02: 00001014 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 26271F40 15:19:07 02: 00001803 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 02FAF080 15:19:07 02: 00001808 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 502D1140 15:19:07 02: 00001814 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 vga 0 rx 36 lo 36 15:19:07 0A: 00000004 15:19:07 02: 00000024 15:19:07 02: 00005000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 00200024 15:19:07 02: 00005000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 0 tx 1 rx 13 15:19:07 0A: 00000004 15:19:07 02: 00000001 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 0000040D 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 1 tx 1 rx 12 15:19:07 0A: 00000004 15:19:07 02: 00000011 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 0000041C 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 2 tx 2 rx 13 15:19:07 0A: 00000004 15:19:07 02: 00000022 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 0000042D 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 3 tx 2 rx 12 15:19:07 0A: 00000004 15:19:07 02: 00000032 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 0000043C 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 4 tx 3 rx 13 15:19:07 0A: 00000004 15:19:07 02: 00000043 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 0000044D 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 5 tx 3 rx 12 15:19:07 0A: 00000004 15:19:07 02: 00000053 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 0000045C 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 6 tx 4 rx 13 15:19:07 0A: 00000004 15:19:07 02: 00000064 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 0000046D 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 7 tx 4 rx 12 15:19:07 0A: 00000004 15:19:07 02: 00000074 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 0000047C 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 8 tx 3 rx 11 15:19:07 0A: 00000004 15:19:07 02: 00000083 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 0000048B 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 9 tx 3 rx 10 15:19:07 0A: 00000004 15:19:07 02: 00000093 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 0000049A 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 10 tx 4 rx 11 15:19:07 0A: 00000004 15:19:07 02: 000000A4 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 000004AB 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 11 tx 4 rx 10 15:19:07 0A: 00000004 15:19:07 02: 000000B4 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 000004BA 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 12 tx 5 rx 11 15:19:07 0A: 00000004 15:19:07 02: 000000C5 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 000004CB 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 13 tx 5 rx 10 15:19:07 0A: 00000004 15:19:07 02: 000000D5 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 000004DA 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 14 tx 6 rx 11 15:19:07 0A: 00000004 15:19:07 02: 000000E6 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 000004EB 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 15 tx 6 rx 10 15:19:07 0A: 00000004 15:19:07 02: 000000F6 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 000004FA 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 16 tx 5 rx 9 15:19:07 0A: 00000004 15:19:07 02: 00000105 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 00000509 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 17 tx 5 rx 8 15:19:07 0A: 00000004 15:19:07 02: 00000115 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 00000518 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 18 tx 6 rx 9 15:19:07 0A: 00000004 15:19:07 02: 00000126 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 00000529 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 19 tx 6 rx 8 15:19:07 0A: 00000004 15:19:07 02: 00000136 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 00000538 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 20 tx 7 rx 9 15:19:07 0A: 00000004 15:19:07 02: 00000147 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 00000549 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 21 tx 7 rx 8 15:19:07 0A: 00000004 15:19:07 02: 00000157 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 00000558 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 22 tx 8 rx 9 15:19:07 0A: 00000004 15:19:07 02: 00000168 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 00000569 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 23 tx 8 rx 8 15:19:07 0A: 00000004 15:19:07 02: 00000178 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 00000578 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 24 tx 7 rx 7 15:19:07 0A: 00000004 15:19:07 02: 00000187 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 00000587 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 25 tx 7 rx 6 15:19:07 0A: 00000004 15:19:07 02: 00000197 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 00000596 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 26 tx 8 rx 7 15:19:07 0A: 00000004 15:19:07 02: 000001A8 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 000005A7 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 27 tx 8 rx 6 15:19:07 0A: 00000004 15:19:07 02: 000001B8 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 000005B6 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 28 tx 9 rx 7 15:19:07 0A: 00000004 15:19:07 02: 000001C9 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 000005C7 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 29 tx 9 rx 6 15:19:07 0A: 00000004 15:19:07 02: 000001D9 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 000005D6 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 30 tx 10 rx 7 15:19:07 0A: 00000004 15:19:07 02: 000001EA 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 000005E7 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 31 tx 10 rx 6 15:19:07 0A: 00000004 15:19:07 02: 000001FA 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 000005F6 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 32 tx 9 rx 5 15:19:07 0A: 00000004 15:19:07 02: 00000209 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 00000605 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 33 tx 9 rx 4 15:19:07 0A: 00000004 15:19:07 02: 00000219 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 00000614 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 34 tx 10 rx 5 15:19:07 0A: 00000004 15:19:07 02: 0000022A 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 00000625 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 35 tx 10 rx 4 15:19:07 0A: 00000004 15:19:07 02: 0000023A 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 00000634 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 36 tx 11 rx 5 15:19:07 0A: 00000004 15:19:07 02: 0000024B 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 00000645 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 37 tx 11 rx 4 15:19:07 0A: 00000004 15:19:07 02: 0000025B 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 00000654 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 38 tx 12 rx 5 15:19:07 0A: 00000004 15:19:07 02: 0000026C 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 00000665 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 39 tx 12 rx 4 15:19:07 0A: 00000004 15:19:07 02: 0000027C 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 00000674 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 40 tx 11 rx 3 15:19:07 0A: 00000004 15:19:07 02: 0000028B 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 00000683 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 41 tx 11 rx 2 15:19:07 0A: 00000004 15:19:07 02: 0000029B 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 00000692 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 42 tx 12 rx 3 15:19:07 0A: 00000004 15:19:07 02: 000002AC 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 000006A3 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 43 tx 12 rx 2 15:19:07 0A: 00000004 15:19:07 02: 000002BC 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 000006B2 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 44 tx 13 rx 3 15:19:07 0A: 00000004 15:19:07 02: 000002CD 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 000006C3 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 45 tx 13 rx 2 15:19:07 0A: 00000004 15:19:07 02: 000002DD 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 000006D2 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 46 tx 14 rx 3 15:19:07 0A: 00000004 15:19:07 02: 000002EE 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 000006E3 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 47 tx 14 rx 2 15:19:07 0A: 00000004 15:19:07 02: 000002FE 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 000006F2 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 48 tx 0 rx 15 15:19:07 0A: 00000004 15:19:07 02: 00000300 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 0000070F 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // ram write 3 sw 49 tx 15 rx 0 15:19:07 0A: 00000004 15:19:07 02: 0000031F 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 0A: 00000004 15:19:07 02: 00000710 15:19:07 02: 00009000 15:19:07 0A: 00000004 15:19:07 15:19:07 // reset seq 15:19:07 08: 00000001 15:19:07 08: 00031000 15:19:07 0E: 00000001 15:19:07 0E: 00000000 15:19:07 15:19:07 // start 15:19:07 0E: 0000000C 15:19:07 0C: 00000001 15:20:04 15:20:04 // reboot trx 3 15:20:04 0A: 00000004 15:20:04 02: 00000001 15:20:04 02: 00019000 15:20:04 0A: 000000FF 15:20:07 15:20:07 // chmod 3 cnt 15:20:07 0A: 00000004 15:20:07 02: 00000001 15:20:07 02: 00039100 15:20:07 0A: 000000FF 15:20:07 15:20:07 // chmod 3 cnt 15:20:07 0A: 00000004 15:20:07 02: 00000001 15:20:07 02: 00039100 15:20:07 0A: 000000FF 15:20:07 15:20:07 // chmod 3 cnt 15:20:07 0A: 00000004 15:20:07 02: 00000001 15:20:07 02: 00039100 15:20:07 0A: 000000FF 15:20:07 15:20:07 // chmod 3 cnt 15:20:07 0A: 00000004 15:20:07 02: 00000001 15:20:07 02: 00039100 15:20:07 0A: 000000FF 15:20:07 15:20:07 // chmod 3 cnt 15:20:07 0A: 00000004 15:20:07 02: 00000001 15:20:07 02: 00039100 15:20:07 0A: 000000FF 15:20:09 15:20:09 // reset mcu 15:20:09 16: 023C3460 15:20:09 17: 00000001 15:20:09 15:20:09 // encoder limit 100 15:20:09 11: 00000064 15:20:09 15:20:09 // encoder virt rate 136691 15:20:09 10: 000215F3 15:20:09 15:20:09 // trx mask 00100000 15:20:09 0A: 00000004 15:20:09 15:20:09 // sched write 0 adc_sample_time freq 62 15:20:09 08: 0000003E 15:20:09 08: 00025000 15:20:09 15:20:09 // sched write 0 adc_sample_time sw 62 15:20:09 08: 0000003E 15:20:09 08: 00029000 15:20:09 15:20:09 // sched write 0 timeout freq 4250 15:20:09 08: 0000109A 15:20:09 08: 0000D000 15:20:09 15:20:09 // sched write 0 timeout freqmaxtomin 11250 15:20:09 08: 00002BF2 15:20:09 08: 00035000 15:20:09 15:20:09 // sched write 0 timeout sw 324 15:20:09 08: 00000144 15:20:09 08: 00011000 15:20:09 15:20:09 // pll write 0 tx 2 2 lo 2 2 15:20:09 08: 02000002 15:20:09 08: 00015000 15:20:09 08: 12000002 15:20:09 08: 00015000 15:20:09 15:20:09 // pll write 0 tx 3 70 lo 3 70 15:20:09 08: 03000046 15:20:09 08: 00015000 15:20:09 08: 13000046 15:20:09 08: 00015000 15:20:09 15:20:09 // pll write 0 tx 4 0 lo 4 2090000 15:20:09 08: 04000000 15:20:09 08: 00015000 15:20:09 08: 141FE410 15:20:09 08: 00015000 15:20:09 15:20:09 // pll write 0 tx 5 0 lo 5 0 15:20:09 08: 05000000 15:20:09 08: 00015000 15:20:09 08: 15000000 15:20:09 08: 00015000 15:20:09 15:20:09 // pll write 0 tx 6 265863 lo 6 265863 15:20:09 08: 06040E87 15:20:09 08: 00015000 15:20:09 08: 16040E87 15:20:09 08: 00015000 15:20:09 15:20:09 // pll write 0 tx 7 1049850 lo 7 1049850 15:20:09 08: 071004FA 15:20:09 08: 00015000 15:20:09 08: 171004FA 15:20:09 08: 00015000 15:20:09 15:20:09 // pll write 0 tx 8 12799 lo 8 12799 15:20:09 08: 080031FF 15:20:09 08: 00015000 15:20:09 08: 180031FF 15:20:09 08: 00015000 15:20:09 15:20:09 // pll write 0 tx 9 2359308 lo 9 2359308 15:20:09 08: 0924000C 15:20:09 08: 00015000 15:20:09 08: 1924000C 15:20:09 08: 00015000 15:20:09 15:20:09 // pll write 0 tx 10 0 lo 10 0 15:20:09 08: 0A000000 15:20:09 08: 00015000 15:20:09 08: 1A000000 15:20:09 08: 00015000 15:20:09 15:20:09 // pll write 0 tx 11 2168 lo 11 2168 15:20:09 08: 0B000878 15:20:09 08: 00015000 15:20:09 08: 1B000878 15:20:09 08: 00015000 15:20:09 15:20:09 // pll write 0 tx 13 1 lo 13 1 15:20:09 08: 0D000001 15:20:09 08: 00015000 15:20:09 08: 1D000001 15:20:09 08: 00015000 15:20:09 15:20:09 // freq write 0 limit 101 15:20:09 08: 00000065 15:20:09 08: 00021000 15:20:09 15:20:09 // freq write 0 vectors_total 1 15:20:09 08: 00000001 15:20:09 08: 0002D000 15:20:09 15:20:09 // freq write 3 span 0 [13500:50:18500] [13525:50:18525] MHz 15:20:09 0A: 00000004 15:20:09 02: 24A9A700 15:20:09 02: 00001003 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 02FAF080 15:20:09 02: 00001008 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 4EAF9900 15:20:09 02: 00001014 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 26271F40 15:20:09 02: 00001803 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 02FAF080 15:20:09 02: 00001808 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 502D1140 15:20:09 02: 00001814 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 vga 0 rx 36 lo 36 15:20:09 0A: 00000004 15:20:09 02: 00000024 15:20:09 02: 00005000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 00200024 15:20:09 02: 00005000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 0 tx 1 rx 13 15:20:09 0A: 00000004 15:20:09 02: 00000001 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 0000040D 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 1 tx 1 rx 12 15:20:09 0A: 00000004 15:20:09 02: 00000011 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 0000041C 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 2 tx 2 rx 13 15:20:09 0A: 00000004 15:20:09 02: 00000022 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 0000042D 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 3 tx 2 rx 12 15:20:09 0A: 00000004 15:20:09 02: 00000032 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 0000043C 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 4 tx 3 rx 13 15:20:09 0A: 00000004 15:20:09 02: 00000043 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 0000044D 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 5 tx 3 rx 12 15:20:09 0A: 00000004 15:20:09 02: 00000053 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 0000045C 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 6 tx 4 rx 13 15:20:09 0A: 00000004 15:20:09 02: 00000064 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 0000046D 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 7 tx 4 rx 12 15:20:09 0A: 00000004 15:20:09 02: 00000074 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 0000047C 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 8 tx 3 rx 11 15:20:09 0A: 00000004 15:20:09 02: 00000083 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 0000048B 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 9 tx 3 rx 10 15:20:09 0A: 00000004 15:20:09 02: 00000093 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 0000049A 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 10 tx 4 rx 11 15:20:09 0A: 00000004 15:20:09 02: 000000A4 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 000004AB 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 11 tx 4 rx 10 15:20:09 0A: 00000004 15:20:09 02: 000000B4 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 000004BA 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 12 tx 5 rx 11 15:20:09 0A: 00000004 15:20:09 02: 000000C5 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 000004CB 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 13 tx 5 rx 10 15:20:09 0A: 00000004 15:20:09 02: 000000D5 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 000004DA 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 14 tx 6 rx 11 15:20:09 0A: 00000004 15:20:09 02: 000000E6 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 000004EB 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 15 tx 6 rx 10 15:20:09 0A: 00000004 15:20:09 02: 000000F6 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 000004FA 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 16 tx 5 rx 9 15:20:09 0A: 00000004 15:20:09 02: 00000105 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 00000509 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 17 tx 5 rx 8 15:20:09 0A: 00000004 15:20:09 02: 00000115 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 00000518 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 18 tx 6 rx 9 15:20:09 0A: 00000004 15:20:09 02: 00000126 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 00000529 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 19 tx 6 rx 8 15:20:09 0A: 00000004 15:20:09 02: 00000136 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 00000538 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 20 tx 7 rx 9 15:20:09 0A: 00000004 15:20:09 02: 00000147 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 00000549 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 21 tx 7 rx 8 15:20:09 0A: 00000004 15:20:09 02: 00000157 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 00000558 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 22 tx 8 rx 9 15:20:09 0A: 00000004 15:20:09 02: 00000168 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 00000569 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 23 tx 8 rx 8 15:20:09 0A: 00000004 15:20:09 02: 00000178 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 00000578 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 24 tx 7 rx 7 15:20:09 0A: 00000004 15:20:09 02: 00000187 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 00000587 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 25 tx 7 rx 6 15:20:09 0A: 00000004 15:20:09 02: 00000197 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 00000596 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 26 tx 8 rx 7 15:20:09 0A: 00000004 15:20:09 02: 000001A8 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 000005A7 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 27 tx 8 rx 6 15:20:09 0A: 00000004 15:20:09 02: 000001B8 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 000005B6 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 28 tx 9 rx 7 15:20:09 0A: 00000004 15:20:09 02: 000001C9 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 000005C7 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 29 tx 9 rx 6 15:20:09 0A: 00000004 15:20:09 02: 000001D9 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 000005D6 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 30 tx 10 rx 7 15:20:09 0A: 00000004 15:20:09 02: 000001EA 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 000005E7 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 31 tx 10 rx 6 15:20:09 0A: 00000004 15:20:09 02: 000001FA 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 000005F6 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 32 tx 9 rx 5 15:20:09 0A: 00000004 15:20:09 02: 00000209 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 00000605 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 33 tx 9 rx 4 15:20:09 0A: 00000004 15:20:09 02: 00000219 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 00000614 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 34 tx 10 rx 5 15:20:09 0A: 00000004 15:20:09 02: 0000022A 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 00000625 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 35 tx 10 rx 4 15:20:09 0A: 00000004 15:20:09 02: 0000023A 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 00000634 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 36 tx 11 rx 5 15:20:09 0A: 00000004 15:20:09 02: 0000024B 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 00000645 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 37 tx 11 rx 4 15:20:09 0A: 00000004 15:20:09 02: 0000025B 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 00000654 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 38 tx 12 rx 5 15:20:09 0A: 00000004 15:20:09 02: 0000026C 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 00000665 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 39 tx 12 rx 4 15:20:09 0A: 00000004 15:20:09 02: 0000027C 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 00000674 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 40 tx 11 rx 3 15:20:09 0A: 00000004 15:20:09 02: 0000028B 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 00000683 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 41 tx 11 rx 2 15:20:09 0A: 00000004 15:20:09 02: 0000029B 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 00000692 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 42 tx 12 rx 3 15:20:09 0A: 00000004 15:20:09 02: 000002AC 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 000006A3 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 43 tx 12 rx 2 15:20:09 0A: 00000004 15:20:09 02: 000002BC 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 000006B2 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 44 tx 13 rx 3 15:20:09 0A: 00000004 15:20:09 02: 000002CD 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 000006C3 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 45 tx 13 rx 2 15:20:09 0A: 00000004 15:20:09 02: 000002DD 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 000006D2 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 46 tx 14 rx 3 15:20:09 0A: 00000004 15:20:09 02: 000002EE 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 000006E3 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 47 tx 14 rx 2 15:20:09 0A: 00000004 15:20:09 02: 000002FE 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 000006F2 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 48 tx 0 rx 15 15:20:09 0A: 00000004 15:20:09 02: 00000300 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 0000070F 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // ram write 3 sw 49 tx 15 rx 0 15:20:09 0A: 00000004 15:20:09 02: 0000031F 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 0A: 00000004 15:20:09 02: 00000710 15:20:09 02: 00009000 15:20:09 0A: 00000004 15:20:09 15:20:09 // reset seq 15:20:09 08: 00000001 15:20:09 08: 00031000 15:20:09 0E: 00000001 15:20:09 0E: 00000000 15:20:09 15:20:09 // start 15:20:09 0E: 0000000C 15:20:09 0C: 00000001 15:20:11 15:20:11 // stop now 15:20:11 0E: 00000004 15:20:12 15:20:12 // reset mcu 15:20:12 16: 023C3460 15:20:12 17: 00000001 15:20:12 15:20:12 // encoder limit 100 15:20:12 11: 00000064 15:20:12 15:20:12 // encoder virt rate 136691 15:20:12 10: 000215F3 15:20:12 15:20:12 // trx mask 00100000 15:20:12 0A: 00000004 15:20:12 15:20:12 // sched write 0 adc_sample_time freq 62 15:20:12 08: 0000003E 15:20:12 08: 00025000 15:20:12 15:20:12 // sched write 0 adc_sample_time sw 62 15:20:12 08: 0000003E 15:20:12 08: 00029000 15:20:12 15:20:12 // sched write 0 timeout freq 4250 15:20:12 08: 0000109A 15:20:12 08: 0000D000 15:20:12 15:20:12 // sched write 0 timeout freqmaxtomin 11250 15:20:12 08: 00002BF2 15:20:12 08: 00035000 15:20:12 15:20:12 // sched write 0 timeout sw 324 15:20:12 08: 00000144 15:20:12 08: 00011000 15:20:12 15:20:12 // pll write 0 tx 2 2 lo 2 2 15:20:12 08: 02000002 15:20:12 08: 00015000 15:20:12 08: 12000002 15:20:12 08: 00015000 15:20:12 15:20:12 // pll write 0 tx 3 70 lo 3 70 15:20:12 08: 03000046 15:20:12 08: 00015000 15:20:12 08: 13000046 15:20:12 08: 00015000 15:20:12 15:20:12 // pll write 0 tx 4 0 lo 4 2090000 15:20:12 08: 04000000 15:20:12 08: 00015000 15:20:12 08: 141FE410 15:20:12 08: 00015000 15:20:12 15:20:12 // pll write 0 tx 5 0 lo 5 0 15:20:12 08: 05000000 15:20:12 08: 00015000 15:20:12 08: 15000000 15:20:12 08: 00015000 15:20:12 15:20:12 // pll write 0 tx 6 265863 lo 6 265863 15:20:12 08: 06040E87 15:20:12 08: 00015000 15:20:12 08: 16040E87 15:20:12 08: 00015000 15:20:12 15:20:12 // pll write 0 tx 7 1049850 lo 7 1049850 15:20:12 08: 071004FA 15:20:12 08: 00015000 15:20:12 08: 171004FA 15:20:12 08: 00015000 15:20:12 15:20:12 // pll write 0 tx 8 12799 lo 8 12799 15:20:12 08: 080031FF 15:20:12 08: 00015000 15:20:12 08: 180031FF 15:20:12 08: 00015000 15:20:12 15:20:12 // pll write 0 tx 9 2359308 lo 9 2359308 15:20:12 08: 0924000C 15:20:12 08: 00015000 15:20:12 08: 1924000C 15:20:12 08: 00015000 15:20:12 15:20:12 // pll write 0 tx 10 0 lo 10 0 15:20:12 08: 0A000000 15:20:12 08: 00015000 15:20:12 08: 1A000000 15:20:12 08: 00015000 15:20:12 15:20:12 // pll write 0 tx 11 2168 lo 11 2168 15:20:12 08: 0B000878 15:20:12 08: 00015000 15:20:12 08: 1B000878 15:20:12 08: 00015000 15:20:12 15:20:12 // pll write 0 tx 13 1 lo 13 1 15:20:12 08: 0D000001 15:20:12 08: 00015000 15:20:12 08: 1D000001 15:20:12 08: 00015000 15:20:12 15:20:12 // freq write 0 limit 101 15:20:12 08: 00000065 15:20:12 08: 00021000 15:20:12 15:20:12 // freq write 0 vectors_total 1 15:20:12 08: 00000001 15:20:12 08: 0002D000 15:20:12 15:20:12 // freq write 3 span 0 [13500:50:18500] [13525:50:18525] MHz 15:20:12 0A: 00000004 15:20:12 02: 24A9A700 15:20:12 02: 00001003 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 02FAF080 15:20:12 02: 00001008 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 4EAF9900 15:20:12 02: 00001014 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 26271F40 15:20:12 02: 00001803 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 02FAF080 15:20:12 02: 00001808 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 502D1140 15:20:12 02: 00001814 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 vga 0 rx 36 lo 36 15:20:12 0A: 00000004 15:20:12 02: 00000024 15:20:12 02: 00005000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 00200024 15:20:12 02: 00005000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 0 tx 1 rx 13 15:20:12 0A: 00000004 15:20:12 02: 00000001 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 0000040D 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 1 tx 1 rx 12 15:20:12 0A: 00000004 15:20:12 02: 00000011 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 0000041C 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 2 tx 2 rx 13 15:20:12 0A: 00000004 15:20:12 02: 00000022 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 0000042D 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 3 tx 2 rx 12 15:20:12 0A: 00000004 15:20:12 02: 00000032 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 0000043C 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 4 tx 3 rx 13 15:20:12 0A: 00000004 15:20:12 02: 00000043 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 0000044D 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 5 tx 3 rx 12 15:20:12 0A: 00000004 15:20:12 02: 00000053 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 0000045C 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 6 tx 4 rx 13 15:20:12 0A: 00000004 15:20:12 02: 00000064 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 0000046D 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 7 tx 4 rx 12 15:20:12 0A: 00000004 15:20:12 02: 00000074 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 0000047C 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 8 tx 3 rx 11 15:20:12 0A: 00000004 15:20:12 02: 00000083 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 0000048B 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 9 tx 3 rx 10 15:20:12 0A: 00000004 15:20:12 02: 00000093 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 0000049A 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 10 tx 4 rx 11 15:20:12 0A: 00000004 15:20:12 02: 000000A4 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 000004AB 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 11 tx 4 rx 10 15:20:12 0A: 00000004 15:20:12 02: 000000B4 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 000004BA 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 12 tx 5 rx 11 15:20:12 0A: 00000004 15:20:12 02: 000000C5 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 000004CB 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 13 tx 5 rx 10 15:20:12 0A: 00000004 15:20:12 02: 000000D5 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 000004DA 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 14 tx 6 rx 11 15:20:12 0A: 00000004 15:20:12 02: 000000E6 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 000004EB 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 15 tx 6 rx 10 15:20:12 0A: 00000004 15:20:12 02: 000000F6 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 000004FA 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 16 tx 5 rx 9 15:20:12 0A: 00000004 15:20:12 02: 00000105 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 00000509 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 17 tx 5 rx 8 15:20:12 0A: 00000004 15:20:12 02: 00000115 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 00000518 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 18 tx 6 rx 9 15:20:12 0A: 00000004 15:20:12 02: 00000126 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 00000529 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 19 tx 6 rx 8 15:20:12 0A: 00000004 15:20:12 02: 00000136 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 00000538 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 20 tx 7 rx 9 15:20:12 0A: 00000004 15:20:12 02: 00000147 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 00000549 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 21 tx 7 rx 8 15:20:12 0A: 00000004 15:20:12 02: 00000157 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 00000558 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 22 tx 8 rx 9 15:20:12 0A: 00000004 15:20:12 02: 00000168 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 00000569 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 23 tx 8 rx 8 15:20:12 0A: 00000004 15:20:12 02: 00000178 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 00000578 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 24 tx 7 rx 7 15:20:12 0A: 00000004 15:20:12 02: 00000187 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 00000587 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 25 tx 7 rx 6 15:20:12 0A: 00000004 15:20:12 02: 00000197 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 00000596 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 26 tx 8 rx 7 15:20:12 0A: 00000004 15:20:12 02: 000001A8 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 000005A7 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 27 tx 8 rx 6 15:20:12 0A: 00000004 15:20:12 02: 000001B8 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 000005B6 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 28 tx 9 rx 7 15:20:12 0A: 00000004 15:20:12 02: 000001C9 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 000005C7 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 29 tx 9 rx 6 15:20:12 0A: 00000004 15:20:12 02: 000001D9 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 000005D6 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 30 tx 10 rx 7 15:20:12 0A: 00000004 15:20:12 02: 000001EA 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 000005E7 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 31 tx 10 rx 6 15:20:12 0A: 00000004 15:20:12 02: 000001FA 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 000005F6 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 32 tx 9 rx 5 15:20:12 0A: 00000004 15:20:12 02: 00000209 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 00000605 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 33 tx 9 rx 4 15:20:12 0A: 00000004 15:20:12 02: 00000219 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 00000614 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 34 tx 10 rx 5 15:20:12 0A: 00000004 15:20:12 02: 0000022A 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 00000625 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 35 tx 10 rx 4 15:20:12 0A: 00000004 15:20:12 02: 0000023A 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 00000634 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 36 tx 11 rx 5 15:20:12 0A: 00000004 15:20:12 02: 0000024B 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 00000645 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 37 tx 11 rx 4 15:20:12 0A: 00000004 15:20:12 02: 0000025B 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 00000654 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 38 tx 12 rx 5 15:20:12 0A: 00000004 15:20:12 02: 0000026C 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 00000665 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 39 tx 12 rx 4 15:20:12 0A: 00000004 15:20:12 02: 0000027C 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 00000674 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 40 tx 11 rx 3 15:20:12 0A: 00000004 15:20:12 02: 0000028B 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 00000683 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 41 tx 11 rx 2 15:20:12 0A: 00000004 15:20:12 02: 0000029B 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 00000692 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 42 tx 12 rx 3 15:20:12 0A: 00000004 15:20:12 02: 000002AC 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 000006A3 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 000002CD 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 000006C3 15:20:12 02: 00009000 15:20:12 0A: 0000000cmd: ram write 3 sw 44 tx 13 rx 3 15:20:12 0A: 00000004 15:20:12 02: 000002CD 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 000006C3 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 45 tx 13 rx 2 15:20:12 0A: 00000004 15:20:12 02: 000002DD 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 000006D2 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 46 tx 14 rx 3 15:20:12 0A: 00000004 15:20:12 02: 000002EE 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 000006E3 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 47 tx 14 rx 2 15:20:12 0A: 00000004 15:20:12 02: 000002FE 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 000006F2 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 48 tx 0 rx 15 15:20:12 0A: 00000004 15:20:12 02: 00000300 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 0000070F 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // ram write 3 sw 49 tx 15 rx 0 15:20:12 0A: 00000004 15:20:12 02: 0000031F 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 0A: 00000004 15:20:12 02: 00000710 15:20:12 02: 00009000 15:20:12 0A: 00000004 15:20:12 15:20:12 // reset seq 15:20:12 08: 00000001 15:20:12 08: 00031000 15:20:12 0E: 00000001 15:20:12 0E: 00000000 15:20:12 15:20:12 // start 15:20:12 0E: 0000000C 15:20:12 0C: 00000001 15:20:55 15:20:55 // adc 3 15:20:55 0A: 00000004 15:20:55 02: 00000004 15:20:55 02: 0001D000 15:20:55 0A: 000000FF