module display();


	reg A;
	reg B;
	reg C;
	

	wire led0;
  	reg led1;
	reg led2;
	reg led3;
	reg led4;
	reg led5;
	reg led6;
	reg led7;
	
	wire notA;
	wire notB; 
	wire notC;
	wire and_one;
	wire and_two;
	wire out1;
	

	
	not U1(notA, A);
	not U2(notB, B);
	not U3(notc, C);
	
	and (and_one,notA,notB);
	and (and_two,notC,B);
	or (led0,and_one,and_two);
	

    initial
    
    	
   
    begin
  	
	 A = 0;
   B = 1;
   C = 1;
  
  #1 $display (led0);
  
   end

endmodule