module Lab2(ClK,KEY,LED);

input ClK;
input [1:0] KEY;
output [27:0] LED;

reg [15:0] counter;
reg [15:0] counterMS; //highest number is 
reg [15:0] value;
reg flag2;

always @(posedge ClK)
begin

	if (KEY[1] == 0)
	begin
		flag2 = 1;

		counter = counter + 1;
	
		if (counter == 50000)
		begin
		
			counter = 16'b0;
		
			counterMS = counterMS + 1;
		end
	end
	
	if (flag2 & (KEY[0] == 0))
	begin
		value = counterMS;
		counterMS = 16'b0;
		flag2 = 0;
	end	
	
	if (~flag2 & (KEY[0]== 0))
	begin
	
	$display("");
	
	end
	
end

initial 
begin

DecimaltoLED first_one(value[3:0] , LED[6:0]);
DecimaltoLED first_one(value[3:0] , LED[6:0]);
DecimaltoLED first_one(value[3:0] , LED[6:0]);
DecimaltoLED first_one(value[3:0] , LED[6:0]);


end



endmodule 


module DecimaltoLED(dec,led);

input [3:0] dec;
output reg[6:0] led;

initial
begin
	case(dec)

		4'b0000: led = 7'b0000000;
		4'b0001: led = 7'b0000000;
		4'b0010: led = 7'b0000000;
		4'b0011: led = 7'b0000000;
		4'b0100: led = 7'b0000000;
		4'b0101: led = 7'b0000000;
		4'b0110: led = 7'b0000000;
		4'b0111: led = 7'b0000000;
		4'b1000: led = 7'b0000000;
		4'b1001: led = 7'b0000000;
		4'b1010: led = 7'b0000000;
		4'b1011: led = 7'b0000000;
		4'b1100: led = 7'b0000000;
		4'b1101: led = 7'b0000000;
		4'b1110: led = 7'b0000000;
		4'b1111: led = 7'b0000000;
		
	
	endcase

end
endmodule
	
	
/*
module counter (C, CLR, Q);
input C, CLR;
output [3:0] Q;
reg [3:0] tmp;


  always @(posedge C or posedge CLR)
    begin
      if (CLR)
        tmp = 4'b0000;
      else
        tmp = tmp + 1'b1;
      end
  assign Q = tmp;
endmodule

endmodule */