list    pe=18f4550,t=ON,c=132,n=80
	Processor	18f4550
	#include <p18f4550.inc>

	__CONFIG	_CONFIG1L, _CPUDIV_OSC1_PLL2_1L & _PLLDIV_5_1L & _USBDIV_2_1L 
	__CONFIG	_CONFIG1H, _FOSC_HSPLL_HS_1H &_FCMEM_OFF_1H & _IESO_OFF_1H 
	__CONFIG	_CONFIG2L, _PWRT_OFF_2L & _BOR_ON_2L & _BORV_2_2L & _VREGEN_ON_2L
	__CONFIG	_CONFIG2H, _WDT_OFF_2H & _WDTPS_32768_2H 
	__CONFIG	_CONFIG3H, _MCLRE_ON_3H & _LPT1OSC_OFF_3H & _PBADEN_ON_3H 
	__CONFIG	_CONFIG4L, _STVREN_ON_4L & _LVP_OFF_4L & _ICPRT_OFF_4L & _XINST_OFF_4L & _DEBUG_OFF_4L 
	__CONFIG	_CONFIG5L, _CP0_OFF_5L & _CP1_OFF_5L
	__CONFIG	_CONFIG5H, _CPB_OFF_5H 
	__CONFIG	_CONFIG6L, _WRT0_OFF_6L & _WRT1_OFF_6L 
	__CONFIG	_CONFIG6H, _WRTB_OFF_6H & _WRTC_OFF_6H 
	__CONFIG	_CONFIG7L, _EBTR0_OFF_7L & _EBTR1_OFF_7L 
	__CONFIG	_CONFIG7H, _EBTRB_OFF_7H 

INIT_CODE	CODE

	clrf	PORTB
	movlw	0Eh
	movlw	0CFh
	movwf	TRISB
	
	end