Reading .arch file: data/prak06.arch Reading .net file: data/s27.net Reading .net file: Parsing Input Block Reading .net file: Blockname: s27_in_2_ Adding Net: [s27_in_2_, ()] Reading .net file: Adding InputBlock [InputBlock s27_in_2_ (0) at (0,0).0] Reading .net file: Parsing Input Block Reading .net file: Blockname: s27_in_1_ Adding Net: [s27_in_1_, ()] Reading .net file: Adding InputBlock [InputBlock s27_in_1_ (0) at (0,0).0] Reading .net file: Parsing Input Block Reading .net file: Blockname: s27_in_3_ Adding Net: [s27_in_3_, ()] Reading .net file: Adding InputBlock [InputBlock s27_in_3_ (0) at (0,0).0] Reading .net file: Parsing Input Block Reading .net file: Blockname: s27_in_0_ Adding Net: [s27_in_0_, ()] Reading .net file: Adding InputBlock [InputBlock s27_in_0_ (0) at (0,0).0] Reading .net file: Parsing Input Block Reading .net file: Blockname: clock Adding Net: [clock, ()] Reading .net file: Adding InputBlock [InputBlock clock (0) at (0,0).0] Reading .net file: Parsing Output Block Reading .net file: Blockname: out:s27_out Adding Net: [s27_out, ()] Reading .net file: Adding OutputBlock [OutputBlock out:s27_out (0) at (0,0).0] Reading .net file: Parsing Logic Block Reading .net file: Blockname: s27_out Reading .net file: Parsing pinlist Reading .net file: Pinlist: [s27_in_3_, n_n41, n_n42, [13], s27_out, open] Adding ports to existing net: [s27_in_3_, ()] Adding Net: [n_n41, ()] Adding Net: [n_n42, ()] Adding Net: [[13], ()] Adding ports to existing net: [s27_out, ()] Reading .net file: Parsing subblocks Reading .net file: Subblocks: [s27_out, 0, 1, 2, 3, 4, open] Reading .net file: Adding LogicBlock [LogicBlock s27_out (0) at (0,0).0] Reading .net file: Parsing Logic Block Reading .net file: Blockname: n_n40 Reading .net file: Parsing pinlist Reading .net file: Pinlist: [s27_in_1_, s27_in_3_, [13], [11], n_n40, clock] Adding ports to existing net: [s27_in_1_, ()] Adding ports to existing net: [s27_in_3_, ()] Adding ports to existing net: [[13], ()] Adding Net: [[11], ()] Adding Net: [n_n40, ()] Adding ports to existing net: [clock, ()] Reading .net file: Parsing subblocks Reading .net file: Subblocks: [n_n40, 0, 1, 2, 3, 4, 5] Reading .net file: Adding LogicBlock [LogicBlock n_n40 (0) at (0,0).0] Reading .net file: Parsing Logic Block Reading .net file: Blockname: n_n41 Reading .net file: Parsing pinlist Reading .net file: Pinlist: [s27_in_3_, [13], open, open, n_n41, clock] Adding ports to existing net: [s27_in_3_, ()] Adding ports to existing net: [[13], ()] Adding ports to existing net: [n_n41, ()] Adding ports to existing net: [clock, ()] Reading .net file: Parsing subblocks Reading .net file: Subblocks: [n_n41, 0, 1, open, open, 4, 5] Reading .net file: Adding LogicBlock [LogicBlock n_n41 (0) at (0,0).0] Reading .net file: Parsing Logic Block Reading .net file: Blockname: n_n42 Reading .net file: Parsing pinlist Reading .net file: Pinlist: [s27_in_3_, n_n42, [13], open, n_n42, clock] Adding ports to existing net: [s27_in_3_, ()] Adding ports to existing net: [n_n42, ()] Adding ports to existing net: [[13], ()] Adding ports to existing net: [n_n42, ()] Adding ports to existing net: [clock, ()] Reading .net file: Parsing subblocks Reading .net file: Subblocks: [n_n42, 0, 1, 2, open, 4, 5] Reading .net file: Adding LogicBlock [LogicBlock n_n42 (0) at (0,0).0] Reading .net file: Parsing Logic Block Reading .net file: Blockname: [13] Reading .net file: Parsing pinlist Reading .net file: Pinlist: [s27_in_2_, s27_in_0_, n_n40, n_n41, [13], open] Adding ports to existing net: [s27_in_2_, ()] Adding ports to existing net: [s27_in_0_, ()] Adding ports to existing net: [n_n40, ()] Adding ports to existing net: [n_n41, ()] Adding ports to existing net: [[13], ()] Reading .net file: Parsing subblocks Reading .net file: Subblocks: [[13], 0, 1, 2, 3, 4, open] Reading .net file: Adding LogicBlock [LogicBlock [13] (0) at (0,0).0] Reading .net file: Parsing Logic Block Reading .net file: Blockname: [11] Reading .net file: Parsing pinlist Reading .net file: Pinlist: [s27_in_2_, n_n40, n_n41, open, [11], open] Adding ports to existing net: [s27_in_2_, ()] Adding ports to existing net: [n_n40, ()] Adding ports to existing net: [n_n41, ()] Adding ports to existing net: [[11], ()] Reading .net file: Parsing subblocks Reading .net file: Subblocks: [[11], 0, 1, 2, open, 4, open] Reading .net file: Adding LogicBlock [LogicBlock [11] (0) at (0,0).0] size: 6 Updating blocks from .p File: data/s27.p Reading .p file: data/s27.p Reading .p file: Array Size: 3,3 Reading .p file: [Block s27_in_2_ (0) at (2,0).1] Reading .p file: [Block s27_in_1_ (1) at (4,2).0] Reading .p file: [Block s27_in_3_ (2) at (3,0).0] Reading .p file: [Block s27_in_0_ (3) at (2,0).0] Reading .p file: [Block clock (4) at (0,2).0] Reading .p file: [Block out:s27_out (5) at (1,0).0] Reading .p file: [Block s27_out (6) at (1,1).0] Reading .p file: [Block n_n40 (7) at (3,2).0] Reading .p file: [Block n_n41 (8) at (3,1).0] Reading .p file: [Block n_n42 (9) at (1,2).0] Reading .p file: [Block [13] (10) at (2,1).0] Reading .p file: [Block [11] (11) at (2,2).0] Checking .p file for valid coordinates Checking that all blocks are placed size: 6 Reading .r file: data/s27.r net 0 s27_in_2_ input source(2,0).1 input opin(2,0).1 Setting port.net to [s27_in_2_, (,,)] chan x(2,0).0 No Channel found at ChannelX at (2,0). Creating it! Routing: Adding to Setting currentVertex to: chan y(1,1).0 net 1 s27_in_1_ input source(4,2).0 input opin(4,2).0 Setting port.net to [s27_in_1_, (,)] chan y(3,2).1 No Channel found at ChannelY at (3,2). Creating it! Error processing s27_in_2_: channels not connected y x. Skipping net. Error processing s27_in_3_: channels not connected y x. Skipping net. Routing: Adding to Setting currentVertex to: logic ipin(3,2).3 Routing: Adding to logic sink(3,2).3 net 2 s27_in_3_ input source(3,0).0 input opin(3,0).0 Setting port.net to [s27_in_3_, (,,,,)] chan x(3,0).0 No Channel found at ChannelX at (3,0). Creating it! Routing: Adding to Setting currentVertex to: chan y(3,1).0 No Channel found at ChannelY at (3,1). Creating it! Routing: Adding to Setting currentVertex to: chan y(3,2).0 Routing: Adding to Setting currentVertex to: chan x(3,2).0 No Channel found at ChannelX at (3,2). Creating it! Routing: Adding to Setting currentVertex to: chan x(2,2).0 No Channel found at ChannelX at (2,2). Creating it! Routing: Adding to Setting currentVertex to: chan x(1,2).0 No Channel found at ChannelX at (1,2). Creating it! Routing: Adding to Setting currentVertex to: chan y(0,2).0 net 3 s27_in_0_ input source(2,0).0 input opin(2,0).0 Setting port.net to [s27_in_0_, (,)] chan x(2,0).1 Routing: Adding to Setting currentVertex to: logic ipin(2,1).0 Routing: Adding to logic sink(2,1).0 net 5 s27_out logic source (1,1).0 logic opin(1,1).0 Setting port.net to [s27_out, (,)] chan x(1,0).1 net 6 n_n41 logic source (3,1).0 logic opin(3,1).0 Setting port.net to [n_n41, (,,,)] chan x(3,0).1 net 7 n_n42 logic source (1,2).3 logic opin(1,2).3 Setting port.net to [n_n42, (,,)] chan x(1,1).1 net 8 [13] logic source (2,1).3 logic opin(2,1).3 Setting port.net to [[13], (,,,,)] chan y(2,1).0 No Channel found at ChannelY at (2,1). Creating it! Routing: Adding to Setting currentVertex to: chan x(2,1).0 No Channel found at ChannelX at (2,1). Creating it! Routing: Adding to Setting currentVertex to: chan x(1,1).0 No Channel found at ChannelX at (1,1). Creating it! Routing: Adding to Setting currentVertex to: logic ipin(1,1).2 Routing: Adding to logic sink(1,1).2 chan x(1,1).0 Setting currentVertex to: logic ipin(1,2).0 Routing: Adding to logic sink(1,2).0 chan y(2,1).0 Setting currentVertex to: chan x(3,1).0 net 9 [11] logic source (2,2).1 logic opin(2,2).1 Setting port.net to [[11], (,)] chan y(2,2).0 No Channel found at ChannelY at (2,2). Creating it! Routing: Adding to Setting currentVertex to: logic ipin(3,2).1 Routing: Adding to logic sink(3,2).1 net 10 n_n40 logic source (3,2).1 logic opin(3,2).1 Setting port.net to [n_n40, (,,)] chan x(3,1).1 size: 6 +----------------------------------------+ | FPGA CONTROL OUTPUT | +----------------------------------------+ *** InputBlocks: *** [InputBlock s27_in_0_ (3) at (2,0).0] [InputBlock s27_in_1_ (1) at (4,2).0] [InputBlock s27_in_2_ (0) at (2,0).1] [InputBlock s27_in_3_ (2) at (3,0).0] CLOCK: [InputBlock clock (4) at (0,2).0] *** Output Blocks: *** [OutputBlock out:s27_out (5) at (1,0).0] *** Logic Blocks: *** [LogicBlock n_n42 (9) at (1,2).0] [LogicBlock [13] (10) at (2,1).0] [LogicBlock n_n40 (7) at (3,2).0] [LogicBlock [11] (11) at (2,2).0] [LogicBlock n_n41 (8) at (3,1).0] [LogicBlock s27_out (6) at (1,1).0] *** Networks: *** Number of networks: 11 [n_n40, (,,)] [n_n42, (,,)] [s27_in_0_, (,)] [s27_in_3_, (,,,,)] [n_n41, (,,,)] [[13], (,,,,)] [s27_in_2_, (,,)] [[11], (,)] [s27_out, (,)] [clock, (,,,)] [s27_in_1_, (,)] Error processing s27_out: invaid chan(1,0).1. Skipping net. Error processing n_n41: invaid chan(3,0).1. Skipping net. Error processing n_n42: invaid chan(1,1).1. Skipping net. Error processing [13]: channels not connected x y. Skipping net. Error processing n_n40: invaid chan(3,1).1. Skipping net. Net 10 (n_n40) -> OutputPort: Net 7 (n_n42) -> OutputPort: Net 3 (s27_in_0_) -> OutputPort: -> Track: -> InputPort: Net 2 (s27_in_3_) -> OutputPort: -> Track: -> Track: -> Track: -> Track: -> Track: -> Track: Net 6 (n_n41) -> OutputPort: Net 8 ([13]) -> OutputPort: -> Track: -> Track: -> Track: -> InputPort: -> InputPort: Net 0 (s27_in_2_) -> OutputPort: -> Track: Net 9 ([11]) -> OutputPort: -> Track: -> InputPort: Net 5 (s27_out) -> OutputPort: Net 0 (clock) -> OutputPort: Net 1 (s27_in_1_) -> OutputPort: -> Track: -> InputPort: Net 10 (n_n40) Visiting OutputPort: Adding to n_n40 Net 7 (n_n42) Visiting OutputPort: Adding to n_n42 Net 3 (s27_in_0_) Visiting OutputPort: Adding to s27_in_0_ Adding to s27_in_0_ Net 2 (s27_in_3_) Visiting OutputPort: Adding to s27_in_3_ Net 6 (n_n41) Visiting OutputPort: Adding to n_n41 Net 8 ([13]) Visiting OutputPort: Adding to [13] Adding to [13] Adding to [13] Net 0 (s27_in_2_) Visiting OutputPort: Adding to s27_in_2_ Net 9 ([11]) Visiting OutputPort: Adding to [11] Adding to [11] Net 5 (s27_out) Visiting OutputPort: Adding to s27_out Net 0 (clock) Visiting Clock's OutputPort Net 1 (s27_in_1_) Visiting OutputPort: Adding to s27_in_1_ Adding to s27_in_1_