`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    19:21:46 11/25/2006 
// Design Name: 
// Module Name:    wphf_m1_5_top 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
//module wphf_m1_5_top(clk, BTN, SW, LD1, LD8, SEG_SEL, SEG_VAL);
module wphf_m1_5_top(clk, BTN, SW, LD1, LD8, SEG_SEL, SEG_VAL, coun_tizesek, coun_egyesek);

	 input clk;
    input [5:3] BTN;
    input [8:3] SW;
	 output LD1;
	 output LD8;
    output [3:0] SEG_SEL;
    output [6:0] SEG_VAL;
	 //teszteléshez
	 output wire [3:0] coun_tizesek;
	 output wire [3:0] coun_egyesek;
	 wire coun_en, orajel, cy_egyesek, cy_tizesek, btn4_ref;
	 //wire [3:0] coun_egyesek;
	 //wire [3:0] coun_tizesek;
	 wire [1:0] status;
	 wire [1:0] seg_selc;
	 wire [3:0] seg_valu;
	 wire ize;
	 
	 always @ (posedge clk)
	 assign ize = coun_en & ~cy_tizesek;
	 
	rategen rategenerator( .clk(clk), .rst(BTN[5]), .cy(orajel) );
	
	szamlalo_mod10 egyesek( .CLK(clk), .RESET(BTN[5]), .CE(ize), .C_E(orajel), .DIN(SW[6:3]), 
		.COUNT(coun_egyesek), .CY(cy_egyesek) );
	
	szamlalo_mod10 tizesek( .CLK(clk), .RESET(BTN[5]), .CE(ize), .C_E(cy_egyesek), .DIN({2'b00,SW[8:7]}),
		.COUNT(coun_tizesek), .CY(cy_tizesek) );
		
	vezerlo_logika vezerlo( .CLK(clk), .CY(cy_tizesek), .btn_reset(BTN[5]), .btn_pausego(btn4_ref),
		.btn_start(BTN[3]), .szamlal(status), .EN(coun_en) ); 
	
	pergesgatlas pergesgatlo( .clk(clk), .btn4(BTN[4]), .btn4_refined(btn4_ref) );
	
	szamlalo_mod4 mod4( .CLK(clk), .RST(BTN[5]), .COUNT(seg_selc) );
	
	dec2to4 segment_select( .CLK(clk), .SEL(seg_selc), .SEG(SEG_SEL) );
	
	mpx4x2to1 segment_ertek( .SEL(seg_selc), .SEG_egyesek(coun_egyesek), .SEG_tizesek(coun_tizesek), 
		.SEG_szazasok({4'b1111}), .SEG_ezresek({4'b1111}), .DOUT(seg_valu) );
	
	seg_dec segment_kod( .clk(clk), .vin(seg_valu), .cry(cy_tizesek), .vout(SEG_VAL) );
	
	assign LD1 = ( status[1] ^ status[0] );
	
	assign LD8 = ( status == 0 );

endmodule