22:25 #ecos: < [TEHb]_> but in some cases, when i do writes like 0xaa and 0x55,
i see some bits, raised to 1, but it's not 0xaa/0x55
22:26 #ecos: < jifl> the chip select would be the most important to find out now
22:26 #ecos: < jifl> see page 589 of ixdp465 manual (i.e. http://download.intel.
com/design/network/manuals/30626204.pdf)
22:26 #ecos: < jifl> you've probably downloaded it already
22:27 #ecos: < [TEHb]_> oh, you mean CE signal
22:27 #ecos: < jifl> finding out that would inform as to whether the problem is
that the memory controller hasn't been set up right at all, as opposed to has be
en setup right, but with the wrong values for this particular DDR.
22:28 #ecos: < [TEHb]_> yes, this signal OK(as said to me hardware guy)
22:28 #ecos: < jifl> If it's the latter, then I'm unlikely to be able to help yo
u.
22:28 #ecos: < jifl> I mean CS_n[0] and CS_n[1]
22:28 -!- Eludias [~eludias@wingding.demon.nl] has joined #kernelnewbies
22:28 #ecos: < jifl> I don't see CE on that page
22:28 #ecos: < jifl> but your schematic may have it labelled differently
22:29 #ecos: < jifl> if that signal is really rising properly when you make an a
ccess, then it's probably the magic numbers for your particular DDR model
22:29 #ecos: < jifl> try setting them to be all as conservative as you can first
 of all
22:29 #ecos: < jifl> perhaps mailing me won't be as useful after all in that cas
e
22:30 #ecos: < jifl> I could help with code problems, not problems with magic va
lues
22:30 #ecos: < jifl> anyway i really gtg
22:30 #ecos: < [TEHb]_> jifl: bye
22:30 #ecos: < jifl> you can reply to this channel - i'll be checking it from ho
me later
22:30 #ecos: < [TEHb]_> ok, thanks :)