library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity top is
        port(
                Cin: in std_logic;
                A: in std_logic_vector (3 downto 0);
                b: in std_logic_vector (3 downto 0);
                s2: in std_logic;
                s1: in std_logic;
                s0: in std_logic;
               	Xout: out std_logic_vector (3 downto 0));
end top;
 
architecture Behavioral of top is
 
component logic_c is
        port (
                  A, B, S0, S1: in STD_LOGIC;
                  Y: out STD_LOGIC
                );
end component;
 
component mux2_1 is
    Port ( Xm, Ym, S2 : in std_logic;
           G : out std_logic);
end component;
 
component fulladd is
        port (
                Af, Bf, Ci, S0f, S1f: in STD_LOGIC;
                C0f, Xf : out STD_LOGIC);
end component;

 
--Logic signals
ArithTemp: std_logic_vector (3 downto 0);
LogicTemp: std_logic_vector (3 downto 0);
CoutTemp:std_logic_vector  (3 downto 0);
                                                                        
begin
CU0: logic_c port map(A(3), B(2), s0, s1, LogicTemp(2));
CU1: logic_c port map(A(2), B(2), s0, s1, LogicTemp(2));
CU2: logic_c port map(A(2), B(2), s0, s1, LogicTemp(2));
CU3: logic_c port map(A(2), B(2), s0, s1, LogicTemp(2));

CU4: fulladd port map(A(3),B(3),Cin,s0,s1,CoutTemp(3),ArithTemp(3));
CU5: fulladd port map(A(2),B(2),CoutTemp(3),s0,s1,CoutTemp(2),ArithTemp(2));
CU6: fulladd port map(A(1),B(1),CoutTemp(2),s0,s1,CoutTemp(1),ArithTemp(1));
CU7: fulladd port map(A(0),B(0),CoutTemp(1),s0,s1,CountTemp(0),ArithTemp(0));

CU8:  mux2_1 port map(ArithTemp(3), LogicTemp(3), sel2, Xout(3));
CU9:  mux2_1 port map(ArithTemp(2), LogicTemp(2), sel2, Xout(2));
CU10: mux2_1 port map(ArithTemp(1), LogicTemp(1), sel2, Xout(1));
CU11: mux2_1 port map(ArithTemp(0), LogicTemp(0), sel2, Xout(0));

 
 
end Behavioral; 

UCF

NET A<3> LOC = P126;  //Slide switches
NET A<2> LOC = P129;
NET A<1> LOC = P133;
NET A<0> LOC = P135;
NET B<3> LOC = P138;
NET B<2> LOC = P140;
NET B<1> LOC = P145;
NET B<0> LOC = P147;

NET X<3> LOC = P154; //LEDs
NET X<2> LOC = P161;
NET X<1> LOC = P163;
NET X<0> LOC = P165;

NET s2 LOC = P149; // Pushbutton switches
NET s1 LOC = P150;
NET s0 LOC = P151;
NET c1 LOC = P152;