-- in architecture -- type ctrl_state is (Halted, S_01, S_02, S_03, S_04, S_05, S_06, S_07, S_08, S_09,S_10,S_11,S_12, Pause_0,Pause_1); signal State, Next_state : ctrl_state; begin Assign_Next_State : process (clk, reset) begin if (Reset = '1') then State <= Halted; elsif (rising_edge(clk)) then State <= Next_State; end if; end process; Get_Next_State : process (State, Opcode, Run, Continue) begin case State is when Halted => if (run = '0') then Next_state <= Halted; else Next_state <= S_18; end if; when S_18 => Next_state <= S_33; when S_33 => Next_state <= S_35; when S_35 => Next_state <= S_32; when S_32 => case Opcode is when "0001" => -- ADD Next_state <= S_01; when "0101" => -- AND Next_state <= S_02; when "1001" => -- NOT Next_state <= S_03; when "0000" => -- BR Next_state <= S_04; when "1100" => -- JMP Next_state <= S_05; when "0100" => -- JSR Next_state <= S_06; when "0110" => -- LDR Next_state <= S_07; when "0111" => -- STR Next_state <= S_10; when "1101" => -- Pause Next_state <= Pause_0; when others => Next_state <= S_18; end case; when S_01 => Next_state <= S_18; when S_02 => Next_state <= S_18; when S_03 => Next_state <= S_18; when S_04 => Next_state <= S_18; when S_05 => Next_state <= S_18; when S_06 => Next_state <= S_18; when S_07 => -- Continue LDR Next_state <= S_08; when S_08 => -- Continue LDR Next_state <= S_09; when S_09 => Next_state <= S_18; when S_10 => -- Continue STR Next_state <= S_11; when S_11 => -- Continue STR Next_state <= S_12; when S_12 => Next_state <= S_18; when Pause_0 => if (Continue = '0') then Next_state <= Pause_1; else Next_state <= Pause_0; end if; when Pause_1 => if (Continue = '1') then Next_state <= S_18; --Done w/ pause else Next_state <= Pause_1; end if; when others => NULL; end case; end process;