Started : "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file "C:/Xilinx/teszt2/teszt2.vhd" in Library work. Entity compiled. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:819 - "C:/Xilinx/teszt2/teszt2.vhd" line 40: The following signals are missing in the process sensitivity list: lcd_counter. Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "C:/Xilinx/teszt2/teszt2.vhd". INFO:Xst:1799 - State operational is never reached in FSM . INFO:Xst:1799 - State third is never reached in FSM . INFO:Xst:1799 - State fourth is never reached in FSM . Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 6 | | Inputs | 4 | | Outputs | 3 | | Clock | clock (rising_edge) | | Power Up State | start | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- WARNING:Xst:737 - Found 4-bit latch for signal . INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefuly review if it was in your intentions to describe such a latch. WARNING:Xst:737 - Found 4-bit latch for signal <$n0024>. INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefuly review if it was in your intentions to describe such a latch. Found 20-bit comparator less for signal <$n0011> created at line 54. Found 20-bit adder for signal <$n0022> created at line 42. Found 1-bit register for signal . Found 25-bit up counter for signal . Found 20-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 21 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 1 Comparator(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Adders/Subtractors : 1 20-bit adder : 1 # Counters : 1 25-bit up counter : 1 # Registers : 2 1-bit register : 1 20-bit register : 1 # Latches : 2 4-bit latch : 2 # Comparators : 1 20-bit comparator less : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Analyzing FSM for best encoding. Optimizing FSM on signal with sequential encoding. ------------------------- State | Encoding ------------------------- start | 00 first | 01 second | 10 third | unreached fourth | unreached operational | unreached ------------------------- ========================================================================= Advanced HDL Synthesis Report Macro Statistics # FSMs : 1 # Adders/Subtractors : 1 20-bit adder : 1 # Counters : 1 25-bit up counter : 1 # Registers : 23 Flip-Flops : 23 # Latches : 2 4-bit latch : 2 # Comparators : 1 20-bit comparator less : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= INFO:Xst:2261 - The FF/Latch <_n0024_1> in Unit is equivalent to the following FF/Latch, which will be removed : <_n0024_0> INFO:Xst:2261 - The FF/Latch <_n0024_3> in Unit is equivalent to the following FF/Latch, which will be removed : <_n0024_2> WARNING:Xst:1710 - FF/Latch <_n0024_3> (without init value) has a constant value of 0 in block . WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : Loading device for application Rf_Device from file '3s500e.nph' in environment C:\Xilinx. Optimizing unit ... Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block teszt2, actual ratio is 1. Latch SF_D_1 has been replicated 1 time(s) to handle iob=true attribute. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s500efg320-5 Number of Slices: 60 out of 4656 1% Number of Slice Flip Flops: 49 out of 9312 0% Number of 4 input LUTs: 107 out of 9312 1% Number of bonded IOBs: 8 out of 232 3% IOB Flip Flops: 2 Number of GCLKs: 1 out of 24 4% ========================================================================= TIMING REPORT Clock Information: ------------------ ----------------------------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | ----------------------------------------------------+------------------------+-------+ clock | BUFGP | 48 | Mcompar__n0011_nor_cyo3(Mcompar__n0011_norcy_rn_2:O)| NONE(*)(_n0024_1) | 1 | _n0035(_n00351:O) | NONE(*)(SF_D_1) | 2 | ----------------------------------------------------+------------------------+-------+ (*) These 2 clock signal(s) are generated by combinatorial logic, and XST is not able to identify which are the primary clock signals. Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic. INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. Timing Summary: --------------- Speed Grade: -5 Minimum period: 6.728ns (Maximum Frequency: 148.629MHz) Minimum input arrival time before clock: No path found Maximum output required time after clock: 8.122ns Maximum combinational path delay: 6.059ns ========================================================================= Process "Synthesize" completed successfully