library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity teszt2 is
    Port
		(
			led : out STD_LOGIC;
			clock : in STD_LOGIC;
			kapcsolo : in STD_LOGIC
		);
end teszt2;

architecture Behavioral of teszt2 is

signal CTR : STD_LOGIC_VECTOR(24 downto 0);
signal allapot: std_logic;

begin
	process( clock )
	begin
		if rising_edge( clock )
		then
			if (CTR="000000")
			then
				if( allapot = '1' ) then
					allapot <= '0';
				else
					allapot <= '1';
				end if;
			end if;
			CTR <= CTR + 1;
			if (CTR = CONV_STD_LOGIC_VECTOR(25000000,25) )
			then 
				CTR<=CONV_STD_LOGIC_VECTOR(0,25);
			end if;
		end if;
	end process;
	led <= allapot and kapcsolo;
end Behavioral;