Started : "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file "C:/Xilinx/teszt2/teszt2.vhd" in Library work. Architecture behavioral of Entity teszt2 is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:819 - "C:/Xilinx/teszt2/teszt2.vhd" line 44: The following signals are missing in the process sensitivity list: lcd_counter. INFO:Xst:1304 - Contents of register in unit never changes during circuit operation. The register is replaced by logic. Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "C:/Xilinx/teszt2/teszt2.vhd". Found finite state machine for signal . ----------------------------------------------------------------------- | States | 8 | | Transitions | 21 | | Inputs | 9 | | Outputs | 8 | | Clock | clock (rising_edge) | | Power Up State | start | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 20-bit comparator less for signal <$n0017> created at line 63. Found 20-bit comparator greater for signal <$n0021> created at line 113. Found 21-bit comparator less for signal <$n0022> created at line 122. Found 20-bit adder for signal <$n0037> created at line 46. Found 1-bit register for signal . Found 25-bit up counter for signal . Found 20-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 21 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 3 Comparator(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Adders/Subtractors : 1 20-bit adder : 1 # Counters : 1 25-bit up counter : 1 # Registers : 2 1-bit register : 1 20-bit register : 1 # Comparators : 3 20-bit comparator greater : 1 20-bit comparator less : 1 21-bit comparator less : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Analyzing FSM for best encoding. Optimizing FSM on signal with speed1 encoding. ------------------------------ State | Encoding ------------------------------ start | 10000000 first | 01000000 second | 00100000 third | 00010000 fourth | 00001000 operational | 00000010 to_clear | 00000100 to_clear_sendcmd | 00000001 ------------------------------ ========================================================================= Advanced HDL Synthesis Report Macro Statistics # FSMs : 1 # Adders/Subtractors : 1 20-bit adder : 1 # Counters : 1 25-bit up counter : 1 # Registers : 29 Flip-Flops : 29 # Comparators : 3 20-bit comparator greater : 1 20-bit comparator less : 1 21-bit comparator less : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Loading device for application Rf_Device from file '3s500e.nph' in environment C:\Xilinx. Optimizing unit ... Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block teszt2, actual ratio is 1. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s500efg320-5 Number of Slices: 81 out of 4656 1% Number of Slice Flip Flops: 54 out of 9312 0% Number of 4 input LUTs: 146 out of 9312 1% Number of bonded IOBs: 11 out of 232 4% Number of GCLKs: 1 out of 24 4% ========================================================================= TIMING REPORT Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clock | BUFGP | 54 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -5 Minimum period: 9.539ns (Maximum Frequency: 104.834MHz) Minimum input arrival time before clock: No path found Maximum output required time after clock: 11.093ns Maximum combinational path delay: 6.059ns ========================================================================= Process "Synthesize" completed successfully Started : "Translate". WARNING:ProjectMgmt - "C:/Xilinx/teszt2/teszt2.ngc" line 0 duplicate design unit: 'Module|teszt2' Command Line: ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc teszt2.ucf -p xc3s500e-fg320-5 teszt2.ngc teszt2.ngd Reading NGO file 'C:/Xilinx/teszt2/teszt2.ngc' ... Applying constraints in "teszt2.ucf" to the design... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Writing NGD file "teszt2.ngd" ... Writing NGDBUILD log file "teszt2.bld"... NGDBUILD done. Process "Translate" completed successfully Started : "Map". Using target part "3s500efg320-5". Mapping design into LUTs... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 54 out of 9,312 1% Number of 4 input LUTs: 105 out of 9,312 1% Logic Distribution: Number of occupied Slices: 82 out of 4,656 1% Number of Slices containing only related logic: 82 out of 82 100% Number of Slices containing unrelated logic: 0 out of 82 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number 4 input LUTs: 150 out of 9,312 1% Number used as logic: 105 Number used as a route-thru: 45 Number of bonded IOBs: 11 out of 232 4% Number of GCLKs: 1 out of 24 4% Total equivalent gate count for design: 1,380 Additional JTAG gate count for IOBs: 528 Peak Memory Usage: 151 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "teszt2_map.mrp" for details. Process "Map" completed successfully Started : "Place & Route". Constraints file: teszt2.pcf. Loading device for application Rf_Device from file '3s500e.nph' in environment C:\Xilinx. "teszt2" is an NCD, version 3.1, device xc3s500e, package fg320, speed -5 Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) Device speed data version: "ADVANCED 1.17 2005-11-04". Design Summary Report: Number of External IOBs 11 out of 232 4% Number of External Input IOBs 2 Number of External Input IBUFs 2 Number of LOCed External Input IBUFs 2 out of 2 100% Number of External Output IOBs 9 Number of External Output IOBs 9 Number of LOCed External Output IOBs 9 out of 9 100% Number of External Bidir IOBs 0 Number of BUFGMUXs 1 out of 24 4% Number of Slices 82 out of 4656 1% Number of SLICEMs 0 out of 2328 0% Overall effort level (-ol): Standard Placer effort level (-pl): High Placer cost table entry (-t): 1 Router effort level (-rl): Standard Starting initial Timing Analysis. REAL time: 4 secs Finished initial Timing Analysis. REAL time: 4 secs Starting Placer Phase 1.1 Phase 1.1 (Checksum:989887) REAL time: 5 secs Phase 2.31 Phase 2.31 (Checksum:1312cfe) REAL time: 5 secs Phase 3.2 ...... .............. Phase 3.2 (Checksum:98a243) REAL time: 9 secs Phase 4.30 Phase 4.30 (Checksum:26259fc) REAL time: 9 secs Phase 5.8 ......... .. ......... . . . Phase 5.8 (Checksum:99cb49) REAL time: 9 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 9 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 9 secs Phase 8.5 Phase 8.5 (Checksum:4c4b3f8) REAL time: 9 secs Writing design to file teszt2.ncd Total REAL time to Placer completion: 9 secs Total CPU time to Placer completion: 8 secs Starting Router Phase 1: 479 unrouted; REAL time: 12 secs Phase 2: 444 unrouted; REAL time: 12 secs Phase 3: 78 unrouted; REAL time: 12 secs Phase 4: 78 unrouted; (0) REAL time: 12 secs Phase 5: 78 unrouted; (0) REAL time: 12 secs Phase 6: 78 unrouted; (0) REAL time: 12 secs Phase 7: 0 unrouted; (0) REAL time: 12 secs Phase 8: 0 unrouted; (0) REAL time: 12 secs Total REAL time to Router completion: 12 secs Total CPU time to Router completion: 11 secs Generating "PAR" statistics. ************************** Generating Clock Report ************************** +---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------+-------------+ | clock_BUFGP | BUFGMUX_X1Y11| No | 32 | 0.041 | 0.146 | +---------------------+--------------+------+------+------------+-------------+ * Net Skew is the difference between the minimum and maximum routing only delays for the net. Note this is different from Clock Skew which is reported in TRCE timing report. Clock Skew is the difference between the minimum and maximum path delays which includes logic delays. Timing Score: 0 Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation. ------------------------------------------------------------------------------------------------------ Constraint | Requested | Actual | Logic | Absolute |Number of | | | Levels | Slack |errors ------------------------------------------------------------------------------------------------------ NET "clock_BUFGP/IBUFG" PERIOD = 20 ns HI | 20.000ns | 9.127ns | 6 | 10.873ns | 0 GH 40% | | | | | ------------------------------------------------------------------------------------------------------ All constraints were met. Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 13 secs Total CPU time to PAR completion: 11 secs Peak Memory Usage: 156 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Timing: Completed - No errors found. Number of error messages: 0 Number of warning messages: 0 Number of info messages: 0 Writing design to file teszt2.ncd PAR done! Process "Place & Route" completed successfully Started : "Generate Post-Place & Route Static Timing". Loading device for application Rf_Device from file '3s500e.nph' in environment C:\Xilinx. "teszt2" is an NCD, version 3.1, device xc3s500e, package fg320, speed -5 Analysis completed Sun Dec 10 16:13:18 2006 -------------------------------------------------------------------------------- Generating Report ... Number of warnings: 0 Total time: 4 secs Process "Generate Post-Place & Route Static Timing" completed successfully Started : "Generate Programming File". Process "Generate Programming File" completed successfully