library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity lcd_component is
	port
	(
		commandId: in std_logic;
		commandValue: in std_logic_vector( 7 downto 0 );
		done: out std_logic;

		clock: in std_logic;
		SF_D: out std_logic_vector( 3 downto 0 );
		LCD_E: out std_logic;
		LCD_RW: out std_logic;
		LCD_RS: out std_logic;		
	);
end lcd_component;

architecture Behavioral of lcd_component is
begin
end Behavioral;