library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity teszt2 is
    Port
		(
			clock : in STD_LOGIC;
			SF_D : out STD_LOGIC_VECTOR(3 downto 0);
			LCD_E : out STD_LOGIC;
			LCD_RW : out STD_LOGIC;
			LCD_RS : out STD_LOGIC;
			SF_CE0 : out STD_LOGIC
		);
end teszt2;

architecture Behavioral of teszt2 is

signal lcd_command_id: std_logic;
signal lcd_command_value: std_logic_vector( 7 downto 0 );
signal lcd_done: std_logic;

component lcd_component is
	port
	(
		commandId: in std_logic;
		commandValue: in std_logic_vector( 7 downto 0 );
		done: out std_logic;

		clock: in std_logic;
		SF_D: out std_logic_vector( 3 downto 0 );
		LCD_E: out std_logic;
		LCD_RW: out std_logic;
		LCD_RS: out std_logic	
	);
end component;

begin
	lcd: lcd_component
	port map
	(
		commandId => lcd_command_id,
		commandValue => lcd_command_value,
		done => lcd_done,
		clock => clock,
		SF_D => SF_D,
		LCD_E => LCD_E,
		LCD_RW => LCD_RW,
		LCD_RS => LCD_RS
	);
	SF_CE0 <= '1';
end Behavioral;