.PHONY: tags clean test

RTL_DIR := rtl/verilog
RTL_OW_DIR := rtl/verilog/1-wire
TB_DIR := bench/verilog

RTL_SOURCE := $(wildcard $(RTL_DIR)/*.v)

TB_SOURCE := $(wildcard $(TB_DIR)/*.v)


# tools used:
# iverilog - Icarus Verilog compiler
# vvp - Icarus Verilog vvp runtime engine

tags:
	ctags -w `find $(RTL_DIR) $(RTL_OW_DIR) $(TB_DIR) \
	\( -name .svn -prune \) -o \( -name '*.[v]' -print \)`

rtl: 	$(RTL_SOURCE)
	iverilog -I$(RTL_DIR) -y$(RTL_DIR) \
	$(RTL_DIR)/cpld_common.v \
	-o cpld.vvp
	touch rtl

tb:	$(RTL_SOURCE) $(TB_SOURCE)
	iverilog -I$(RTL_DIR) -y$(RTL_DIR) -y$(TB_DIR) \
	$(TB_DIR)/tst_bench_top.v \
	-o tb.vvp
	touch tb

tb_sim:	tb
	vvp tb.vvp	
	touch tb_sim

wave: 	tb_sim
	gtkwave sim.vcd traces.wav

clean:
	rm sim/rtl_sim/out/*.vvp