always @(MA_i, BA_i, M_CS4_n_i, MOE_n_i, 
			BC_PWR, ENET_SLP_n_o, ETH_RESET_o, USB_RST_n_o, VCC5_EN_o,
			bkup_chg_en, CH_M_n_i, CH_B_n_i, CH_PRES_M_n_i, BKLT_ENABLE_o, LCD_ENABLE_o, LCD_PWR_o,
			PC0_RST_o, pc0_v3_n, pc0_v5_n, pc0_cd_n, PC0_VS1_i, PC0_VS0_i,
			PC1_RST_o, pc1_v3_n, pc1_v5_n, pc1_cd_n, PC1_CD2_n_i, PC1_VS1_i, PC1_VS0_i,
			PC_VERR_n_i,
			BT_LINK_STAT_i, BT_RESET_o, BT_POWER_o,
			CART_PWR0_o, SD_WP0_i, SD_PWR0_o,
		   cpld_irq_en_reg, opto_irq_en_reg, bt_irq_en_reg, pc0_skt_irq_en_reg,
		   opto_irq_reg, bt_irq_reg, pc0_skt_irq_reg,
		   IR_MODE_o, IR_SD_MODE_o, PRNTR_RD_o)

begin
	case (MA_i)
		'b000: begin
			case (BA_i)
				'b000: begin
					// PWR_RST_CTL
					data_int[7] = BC_PWR;
					data_int[6] = PRNTR_RD_o;
					data_int[5] = IR_SD_MODE_o;
					data_int[4] = IR_MODE_o;
					data_int[3] = ENET_SLP_n_o;
					data_int[2] = ETH_RESET_o;
					data_int[1] = USB_RST_n_o;
					data_int[0] = VCC5_EN_o;
				end
				'b010: begin
					// LCD_CTL
					data_int[7] = bkup_chg_en;
					data_int[6] = CH_B_n_i;
					data_int[5] = CH_M_n_i;
					data_int[4] = CH_PRES_M_n_i;
					data_int[3] = 'b0;
					data_int[2] = BKLT_ENABLE_o;
					data_int[1] = LCD_ENABLE_o;
					data_int[0] = LCD_PWR_o;
				end
	
....

And then drive the data_int signal onto the external pins only when we
have a read.  This part should definitely be async as you are only
driving the bus when you are supposed to.

assign BD_io = (M_CS4_n_i == 0 && MOE_n_i == 0) ? data_int : 'bz;