reg [5:0] Zd;
always @(posedge clk) Zd <= {Zd[4:0], Z};

wire good_one = Zd == 6'b111111;
wire good_zero = Zd == 6'b000000;
reg last_good;

wire index_pulse = good_one && ! last_good;

always @(posedge clk)
begin
    if(good_one) last_good <= 1;
    else if(good_zero) last_good <= 0;
end