/*
 * nForce PCI config space registers.
 */
#define PCI_IDE_ENABLE      0x50
#define PCI_IDE_CONFIG      0x51
#define PCI_CABLE_DETECT	0x52
#define PCI_FIFO_CONFIG     0x53
#define PCI_DATA_TIMING     0x58
#define PCI_CMD_TIMING      0x5e
#define PCI_ADDRESS_SETUP   0x5c
#define PCI_ULTRA_TIMING    0x60

.......

/*
 * Properties for each virtual timing register.
 */
static const struct {
    UInt8  bitmask;
    UInt8  bitnum;
    UInt8  minValue;
    UInt8  maxValue;
} TimingRegInfo[ kTimingRegCount ] =
{
    { 0x0F, 4, 1, 16 },  /* kTimingRegCommandActive */
    { 0x0F, 0, 1, 16 },  /* kTimingRegCommandRecovery */
    { 0x0F, 4, 1, 16 },  /* kTimingRegDataActive */
    { 0x0F, 0, 1, 16 },  /* kTimingRegDataRecovery */
    { 0x03, 6, 1,  4 },  /* kTimingRegAddressSetup */
    { 0xFF, 0, 0,  0 }   /* kTimingRegUltra */
};

/*---------------------------------------------------------------------------
 *
 * PIO
 *
 ---------------------------------------------------------------------------*/

static const TimingParameter PIOTimingTable[ kPIOModeCount ] =
{
   /* Cycle  Setup  Act    Rec */
    { 600,    70,   290,   310 },
    { 383,    50,   290,    93 },
    { 240,    30,   290,    50 },
    { 180,    30,    90,    90 }, 
    { 120,    25,    75,    45 }
};

/*---------------------------------------------------------------------------
 *
 * Multi-word DMA
 *
 ---------------------------------------------------------------------------*/

static const TimingParameter DMATimingTable[ kDMAModeCount ]=
{
   /* Cycle  Setup   tD     tK */
    { 480,    70,   240,   240 },
    { 150,    50,    90,    60 },
    { 120,    30,    75,    45 }
};

/*---------------------------------------------------------------------------
 *
 * Ultra DMA
 *
 ---------------------------------------------------------------------------*/

static const UInt8 UltraTimingTable[kUltraModeCount] =
{
/* UDMA  0     1     2     3     4     5     6 */
      0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7
};

#endif /* !_APPLENVIDIANFORCETIMING_H */