entity zaehler is
	generic (
		bits: natural:=5
	);
   Port ( clk : in  STD_LOGIC;
           s : in  STD_LOGIC;
           Q : out  STD_LOGIC_VECTOR (bits-1 downto 0);
			  D: in STD_LOGIC_VECTOR (bits-1 downto 0)
	);
end zaehler;

architecture Behavioral of zaehler is
signal cnt:  STD_LOGIC_VECTOR(bits-1 downto 0);
signal set:  STD_LOGIC:='0';
signal temp: STD_LOGIC_VECTOR(bits-1 downto 0);

begin
	process(s)
	begin
		if rising_edge(s) then
			set<='1';
			temp<=D;
		end if;
		if cnt=temp then
			set<='0';
		end if;
	end process;
	
	process(clk)
	begin
		if rising_edge(clk) then
			if set='1' then
				cnt<=temp;
			else
				cnt<=cnt+1;
			end if;
		end if;
	end process;

	Q<=cnt;
end Behavioral;