LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY demi_add IS
	PORT (
		x1 : IN STD_LOGIC;
		x2 : IN STD_LOGIC;
		y : OUT STD_LOGIC;
		c_out : OUT STD_LOGIC
		);
END demi_add;

ARCHITECTURE arch_flot OF demi_add IS

COMPONENT xor_2
	PORT(
		a : IN STD_LOGIC;
		b : IN STD_LOGIC;
		r : OUT STD_LOGIC
		);
END COMPONENT;

COMPONENT and_2
	PORT(
		a : IN STD_LOGIC;
		b : IN STD_LOGIC;
		r : OUT STD_LOGIC
		);
END COMPONENT;

BEGIN
	u1 : xor_2 PORT MAP (a => x1,
						 b => x2,
						 r => c_out);						
	u2 : and_2 PORT MAP (a => x1,
					b => x2,
					r => y);
END arch_flot;