LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY fa IS
    PORT (
		a : IN STD_LOGIC;
		b : IN STD_LOGIC;
		c_in : IN STD_LOGIC;
		sum : OUT STD_LOGIC;
		c_out : OUT STD_LOGIC
		);
END fa;

ARCHITECTURE arch_fa OF fa IS

BEGIN

sum <= (a XOR b XOR c_in);
c_out <= ((a AND b) OR (c_in AND a) OR (c_in AND b) or (c_in AND a AND b));

END arch_fa;