module RF(RW,SA,SB,DR,D_in,DataA,DataB,reset);

input [2:0] DR,SA,SB;
input RW, reset;
input [7:0] D_in;
output [7:0] DataA, DataB;

reg [7:0] Mem[7:0], DataA, DataB;

always @ (SA)
case (SA)
	3'b000: DataA <= Mem[0];
	3'b001: DataA <= Mem[1];
	3'b010: DataA <= Mem[2];
	3'b011: DataA <= Mem[3];
	3'b100: DataA <= Mem[4];
	3'b101: DataA <= Mem[5];
	3'b110: DataA <= Mem[6];
	3'b111: DataA <= Mem[7];
endcase

always @ (SB)
case (SB)
	3'b000: DataB <= Mem[0];
	3'b001: DataB <= Mem[1];
	3'b010: DataB <= Mem[2];
	3'b011: DataB <= Mem[3];
	3'b100: DataB <= Mem[4];
	3'b101: DataB <= Mem[5];
	3'b110: DataB <= Mem[6];
	3'b111: DataB <= Mem[7];
endcase

always @ (D_in,reset)
begin
if(RW==1) begin
case (DR) 
	3'b000: Mem[0] <= D_in;
	3'b001: Mem[1] <= D_in;
	3'b010: Mem[2] <= D_in;
	3'b011: Mem[3] <= D_in;
	3'b100: Mem[4] <= D_in;
	3'b101: Mem[5] <= D_in;
	3'b110: Mem[6] <= D_in;
	3'b111: Mem[7] <= D_in;
endcase
end
if (reset==1) begin
Mem[0] <= 8'b00000000;
Mem[1] <= 8'b00000000;
Mem[2] <= 8'b00000000;
Mem[3] <= 8'b00000000;
Mem[4] <= 8'b00000000;
Mem[5] <= 8'b00000000;
Mem[6] <= 8'b00000000;
Mem[7] <= 8'b00000000;
end
end

endmodule