module pc_comp(nxt_pc, cur_pc, clock, reset, startPC, nPCsel, zero, jump, immed, inst);

	input [31:0] startPC;
	input [31:0] cur_pc;
	input reset, clock, nPCsel, zero, jump;
	input [31:0] immed; //already extended for branch
	input [31:0] inst;  //needed for jump

	output [31:0] nxt_pc;

	reg [31:0] nxt_pc, immed_reg;
	reg branch;
	reg [27:0] shifted_inst;

	always@(negedge reset)
		nxt_pc = startPC;

	always@(negedge clock)
	begin
		if( reset == 1)
		begin
			branch = nPCsel & zero;
			immed_reg = immed;
			nxt_pc = cur_pc+4;	//always happens if reset = 1

			if (jump ==1)	//jump signal takes precedence over branch
			begin
				shifted_inst[27:2] = inst[25:0];
				shifted_inst[1] = 0;
				shifted_inst[0] = 0;
				nxt_pc[27:0] = shifted_inst[27:0];
			end //end jump=1
			
			else
			begin
				if (branch == 1) //if nPCsel and zero = 1
				begin
					immed_reg = immed_reg << 2;
					nxt_pc = nxt_pc + immed_reg;
				end //end branch

			end //end else
		end //end reset == 1
	end //end negedge clock
endmodule


/*module m555 (CLK);
   parameter StartTime = 0, Ton = 50, Toff = 50, Tcc = Ton+Toff; // 
 
   output CLK;
   reg 	  CLK;
   
   initial begin
      #StartTime CLK = 0;
   end
   
   // The following is correct if clock starts at LOW level at StartTime //
   always begin
      #Toff CLK = ~CLK;
      #Ton CLK = ~CLK;
   end
endmodule


module testPC ( nxt_pc, cur_pc, clock, reset, startPC, nPCsel, zero, jump, immed, inst);
	input [31:0] nxt_pc;
	input clock;

	output [31:0] startPC, cur_pc;
	output reset, nPCsel, zero, jump;
	output [31:0] immed;
	output [31:0] inst;

	reg [31:0] startPC, cur_pc;
	reg reset, nPCsel, zero, jump;
	reg [31:0] immed;
	reg [31:0] inst;

	initial begin
		$monitor ( $time, " clock=%b, nxt_pc=%8h, cur_pc=%8h, reset=%b, startPC=%8h, nPCsel=%b, zero=%b, jump=%b, immed=%8h, inst=%8h",
			 clock, nxt_pc, cur_pc, reset, startPC, nPCsel, zero, jump, immed, inst);

		#200
		cur_pc = 32'h00000000; reset = 1; startPC = 32'hFFFFFFFF; nPCsel = 0; zero = 0; jump = 0;
		immed = 32'h0000000; inst = 32'h00000000; //should return 4

		#200
		cur_pc = 32'h00000004; reset = 1; startPC = 32'hFFFFFFFF; nPCsel = 1; zero = 1; jump = 0;
		immed = 32'h00000002; inst = 32'h10000002; //should return 16

		#200
		cur_pc = 32'h00000004; reset = 1; startPC = 32'hFFFFFFFF; nPCsel = 1; zero = 0; jump = 0;
		immed = 32'h00000002; inst = 32'h10000002; //should return 8

		#200
		cur_pc = 32'h00000004; reset = 1; startPC = 32'hFFFFFFFF; nPCsel = 0; zero = 1; jump = 0;
		immed = 32'h00000002; inst = 32'h10000002; //should return 8

		#200
		cur_pc = 32'h1000000C; reset = 1; startPC = 32'hFFFFFFFF; nPCsel = 0; zero = 0; jump = 1;
		immed = 32'h00000002; inst = 32'h08000002; //should return 8

		#200
		cur_pc = 32'h00000004; reset = 0; startPC = 32'hFFFFFFFF; nPCsel = 1; zero = 1; jump = 0;
		immed = 32'h00000002; inst = 32'h10000002; //should return all 1s

		#200
		$finish;
	end
endmodule

module testBench;
	wire clock;
	wire [31:0] startPC, cur_pc, nxt_pc;
	wire reset, nPCsel, zero, jump;
	wire [31:0] immed;
	wire [31:0] inst;
	
	m555(clock);
	pc_comp(nxt_pc, cur_pc, clock, reset, startPC, nPCsel, zero, jump, immed, inst);
	testPC(nxt_pc, cur_pc, clock, reset, startPC, nPCsel, zero, jump, immed, inst);
endmodule*/