class StepDriver:
    ID_CODE = 10
    NUM_REGS = 4

    Pre_Fpga_Vars()
    step_up_phA = Range(0, 72, __doc__="connect stepgen $INSTANCE Step/Up/PhaseA output to pin number?")
    dir_down_phB = Range(0, 72, __doc__="connect stepgen $INSTANCE Dir/Down/PhaseB output to pin number?")

    Post_Fpga_Vars()
    enable = Enum("no", "yes", __doc__="...")
    ctrl_type = Enum("velocity", "position", __doc__="...")
    step_type = Enum("step-dir", "up-down", "quadrature", __doc__="...")

    VHDL_TEMPLATE="""
stepgen_${INSTANCE}: stepgen
    port map (
        clock => lclk,
        enable => one,
        ibus => wr_bus,
        obus => rd_bus,
        sel => ${CS},
        write => write,
        read => read,
        addr => ${ADDRESS},
        out0 => iobits.out(${step_up_phA}),
        out1 => iobits.out(${dir_down_phB})
    );
"""

    RAM_TEMPLATE="""
${ID_CODE}
${INSTANCE}
${BASEADDR>>8}
${BASEADDR}
${ctrl_type} | ${step_type}<<2
${step_up_phA}
${dir_down_phB}
"""