library ieee;
use ieee.std_logic_1164.all;
	
entity binary_clock is
port(
	clk : in bit; 
	seg_o, min_o, hora_o : out integer);
end binary_clock;
	
architecture behavior of binary_clock is
signal seg,hora,min : integer := 0;
begin
	process (clk)
	 begin
		if (clk'event and clk = '1') then
			seg <= seg + 1;
			seg_o <= seg;
		end if;
			
		if (seg = 60) then
			seg <= 0;
			min <= min + 1;
			min_o <= min;
		end if;
		
		if (min = 60) then
			min <= 0;
			hora <= hora + 1;
			hora_o <= hora;
		end if;
		
		if (hora = 24) then
			hora <= 0;
		end if;
	end process;
end behavior;