`timescale 10us / 10ns

module keyboard_driver_test(DRV_OUT, B);


// This test module is wrote
// in the following scenario: the driver is on the FPGA and the keyboard
// is attached to the FPGA development board



// Declaration
output [7:0] DRV_OUT;
output B;

// This signals must explicitly added to the simulation.

// For debugging purposes, also add the register named "i" from the keyboard driver

reg DRV_RESET;

reg KBD_CLK_LINE, KBD_DATA_LINE;
wire DRV_OUT;




keyboard_hw_driver kd (
	DRV_RESET, 
	KBD_CLK_LINE, KBD_DATA_LINE, 
	DRV_OUT, B);



// Reset the driver by using the reset button of the FPGA board.

initial begin

	DRV_RESET = 0;
	#1;

	DRV_RESET = 1;

	#1;

	DRV_RESET = 0;	

end



// Now, simulate the keyboard.

// Consider the keyboard clock period to be about 100 units.

initial begin

	// At the begining, the line idle for some periods.
	KBD_CLK_LINE=1; KBD_DATA_LINE=1; #100; #100; 

	//Trimitem L_SHIFT

	// Send start bit.

	KBD_CLK_LINE=1; #25; KBD_DATA_LINE=0; #25; KBD_CLK_LINE=0; #50;

	// Send the scan code

	KBD_CLK_LINE=1; #25; KBD_DATA_LINE=0; #25; KBD_CLK_LINE=0; #50;
	KBD_CLK_LINE=1; #25; KBD_DATA_LINE=1; #25; KBD_CLK_LINE=0; #50;
	KBD_CLK_LINE=1; #25; KBD_DATA_LINE=0; #25; KBD_CLK_LINE=0; #50;
	KBD_CLK_LINE=1; #25; KBD_DATA_LINE=0; #25; KBD_CLK_LINE=0; #50;
	KBD_CLK_LINE=1; #25; KBD_DATA_LINE=1; #25; KBD_CLK_LINE=0; #50;
	KBD_CLK_LINE=1; #25; KBD_DATA_LINE=0; #25; KBD_CLK_LINE=0; #50;
	KBD_CLK_LINE=1; #25; KBD_DATA_LINE=0; #25; KBD_CLK_LINE=0; #50;
	KBD_CLK_LINE=1; #25; KBD_DATA_LINE=0; #25; KBD_CLK_LINE=0; #50;
	// Send the parity bit which is '1' for the 'a' key.

	KBD_CLK_LINE=1; #25; KBD_DATA_LINE=1; #25; KBD_CLK_LINE=0; #50;
	// Send the stop bit.
	KBD_CLK_LINE=1; #25; KBD_DATA_LINE=1; #25; KBD_CLK_LINE=0; #50;
	// Put the line idle for two periods.

	// When a key is pressed, the keyboard sends its scan code

	// on the data line. For the 'a' key, the scan code is 1Ch=00011100b.

	// The order is LSb first, so the bits are sent in the following order: 00111000.

	// Simulate pressing the 'a' key.

	// Send start bit.

	KBD_CLK_LINE=1; #25; KBD_DATA_LINE=0; #25; KBD_CLK_LINE=0; #50;

	// Send the scan code

	KBD_CLK_LINE=1; #25; KBD_DATA_LINE=0; #25; KBD_CLK_LINE=0; #50;
	KBD_CLK_LINE=1; #25; KBD_DATA_LINE=0; #25; KBD_CLK_LINE=0; #50;
	KBD_CLK_LINE=1; #25; KBD_DATA_LINE=1; #25; KBD_CLK_LINE=0; #50;
	KBD_CLK_LINE=1; #25; KBD_DATA_LINE=1; #25; KBD_CLK_LINE=0; #50;
	KBD_CLK_LINE=1; #25; KBD_DATA_LINE=1; #25; KBD_CLK_LINE=0; #50;
	KBD_CLK_LINE=1; #25; KBD_DATA_LINE=0; #25; KBD_CLK_LINE=0; #50;
	KBD_CLK_LINE=1; #25; KBD_DATA_LINE=0; #25; KBD_CLK_LINE=0; #50;
	KBD_CLK_LINE=1; #25; KBD_DATA_LINE=0; #25; KBD_CLK_LINE=0; #50;
	// Send the parity bit which is '1' for the 'a' key.

	KBD_CLK_LINE=1; #25; KBD_DATA_LINE=1; #25; KBD_CLK_LINE=0; #50;
	// Send the stop bit.
	KBD_CLK_LINE=1; #25; KBD_DATA_LINE=1; #25; KBD_CLK_LINE=0; #50;
	// Put the line idle for two periods.

	KBD_CLK_LINE=1; KBD_DATA_LINE=1; #100; #100;

	

	// When the 'a' key - that is now pressed,

	// will be released, then the keyboard will send F0h, 1Ch.

	// We do not simulate this because the process is similar.

end



endmodule