library ieee;
use ieee.std_logic_1164.all;
	
entity binary_clock is
port(
	clk : in bit; 
	seg_o, min_o, hora_o : out integer);
end binary_clock;
	
architecture behavior of binary_clock is
signal seg,hora,min : integer := 0;
begin
	seg_o <= seg;
	min_o <= min;
	hora_o <= hora;
	process (clk)
	 begin
		if (clk'event and clk = '1') then
			if (seg = 59) then
				seg <= 0;
				if (min = 59) then
					min <= 0;
					if (hora = 23) then
						hora <= 0;
					else
						hora <= hora + 1;
					end if;
				else
					min <= min + 1;
				end if;
			else
				seg <= seg + 1;
			end if;
		end if;
	end process;
end behavior;