ROM:A0021020 ; ---------------------------------------------------------------------------
ROM:A0021020 ; START
ROM:A0021020 ; CPSR Regs
ROM:A0021020 ;   31 30 29 28  ---   7   6   -   4   3   2   1   0
ROM:A0021020 ;   N  Z  C  V         I   F       M4  M3  M2  M1  M0
ROM:A0021020 ; ---------------------------------------------------------------------------
ROM:A0021020                 MRS     R1, CPSR		; R1 = CPSR
ROM:A0021024                 BIC     R1, R1, #0x1F	; R1 &= ~0x1F (11111)
ROM:A0021028                 ORR     R1, R1, #0xD3	; R1 |= 0xD3  (11010011)
ROM:A002102C                 MSR     CPSR_cf, R1	; CPSR = R1
ROM:A0021030                 LDR     R0, =0x50078	; R0 = 0x50078      F    B    7    3
ROM:A0021034                 MCR     p15, 0, R0,c1,c0	; Sets MMU to (0101 0000 0000 0111 1000)
Rom:A0021038                 MOV     R1, #0		; R1 = 0          3    7    B    F  
ROM:A002103C                 MCR     p15, 0, R1,c7,c5	; Invalidate I cache
ROM:A0021040                 MCR     p15, 0, R1,c7,c6	; Invalidate D cache
ROM:A0021044                 MCR     p15, 0, R1,c7,c10,4; Drain write buffer
ROM:A0021048                 MOV     R1, #0xF0000000	; R1 = 0xF0000000
ROM:A002104C                 LDR     R0, =0x400700	; R0 = *0x400700
ROM:A0021050                 STR     R0, [R1,#0xC0]	; *(R1 + 0xC0) = R0
ROM:A0021054                 LDR     R0, =0x81F84911	; R0 = *0x81F84911
ROM:A0021058                 STR     R0, [R1,#0x100]	; *(R1 + 0x100) = R0
ROM:A002105C                 LDR     R0, =0xB0000051	; R0 = *0xB0000051
ROM:A0021060                 STR     R0, [R1,#0x88]	; *(R1 + 0x88) = R0
ROM:A0021064                 LDR     R0, =0x402700	; R0 = *0x402700
ROM:A0021068                 STR     R0, [R1,#0xC8]	; *(R1 + 0xC8) = R0
ROM:A002106C                 LDR     R0, =0x80904911	; R0 = *0x80904911
ROM:A0021070                 STR     R0, [R1,#0x108]	; *(R1 + 0x108) = R0
ROM:A0021074                 BL      peripheral_configa	; Peripheral bus config
ROM:A0021078                 BL      func_init_assigned_vars	; Initialize vars and tables
ROM:A0021078
ROM:A002107C                 LDR     R0, =(loc_A00215F8+1) ; Jump to A00215F8
ROM:A0021080                 BX      R0