uint32_t l1r0 = 0, l1r1 =0;
    l1r0 = mfspr(SPRN_L1CSR0);
    l1r1 = mfspr(SPRN_L1CSR1);
  
    /* invalidate d-cache */
    asm ("msync; isync;");
    mtspr(SPRN_L1CSR0, (l1r0 | L1CSR0_CFI));
    asm ("isync;");
    /* disable d-cache */
    mtspr(SPRN_L1CSR0, (l1r0 & ~L1CSR0_DCE));

    /* invalidate icache */
    mtspr(SPRN_L1CSR1, (l1r1 | L1CSR1_ICFI));
    asm("isync;");

    /* disable icache */
    mtspr(SPRN_L1CSR1, (l1r1 & ~L1CSR1_ICE));
    asm ("isync;");