static INLINE void init_chip(int mode)
{
#if !defined(ENABLE_HARDWARE_EMULATION) || !ENABLE_HARDWARE_EMULATION
    //  Enable PPE in PMU
    *(unsigned long *)0xBF10201C &= ~((1 << 13) | (1 << 15));
    
  #if defined(DEBUG_WRITE_GPIO_REGISTER) && DEBUG_WRITE_GPIO_REGISTER
    *(unsigned long *)0xBE100B1C = (*(unsigned long *)0xBE100B1C & 0x00009859) | 0x00006786;
    *(unsigned long *)0xBE100B20 = (*(unsigned long *)0xBE100B20 & 0x00009859) | 0x000067a6;
    *(unsigned long *)0xBE100B4C = (*(unsigned long *)0xBE100B4C & 0x00000fa7) | 0x0000e058;
    *(unsigned long *)0xBE100B50 = (*(unsigned long *)0xBE100B50 & 0x00000fa7) | 0x0000f058;
    
    if ( mode != REV_MII_MODE )
    {
        *(unsigned long *)0xBE100B18 = (*(unsigned long *)0xBE100B18 & 0x00009859) | 0x00006020;
        *(unsigned long *)0xBE100B48 = (*(unsigned long *)0xBE100B48 & 0x00000fa7) | 0x00007000;
        *(unsigned long *)0xBE100B24 = *(unsigned long *)0xBE100B24 | 0x00006020;
        *(unsigned long *)0xBE100B54 = *(unsigned long *)0xBE100B54 | 0x00007000;
        dbg("MII_MODE");
    }
    else
    {
        *(unsigned long *)0xBE100B18 = (*(unsigned long *)0xBE100B18 & 0x00009859) | 0x00000786;
        *(unsigned long *)0xBE100B48 = (*(unsigned long *)0xBE100B48 & 0x00000fa7) | 0x00008058;
        *(unsigned long *)0xBE100B24 = *(unsigned long *)0xBE100B24 | 0x00000786;
        *(unsigned long *)0xBE100B54 = *(unsigned long *)0xBE100B54 | 0x00000058;
        dbg("REV_MII_MODE");
    }

    dbg("DANUBE_GPIO_P0_ALTSEL0(0xBE100B1C) = 0x%08X", *(unsigned int *)0xBE100B1C);
    dbg("DANUBE_GPIO_P0_ALTSEL1(0xBE100B20) = 0x%08X", *(unsigned int *)0xBE100B20);
    dbg("DANUBE_GPIO_P1_ALTSEL0(0xBE100B4C) = 0x%08X", *(unsigned int *)0xBE100B4C);
    dbg("DANUBE_GPIO_P1_ALTSEL1(0xBE100B50) = 0x%08X", *(unsigned int *)0xBE100B50);
    dbg("DANUBE_GPIO_P0_DIR(0xBE100B18)     = 0x%08X", *(unsigned int *)0xBE100B18);
    dbg("DANUBE_GPIO_P1_DIR(0xBE100B48)     = 0x%08X", *(unsigned int *)0xBE100B48);
    dbg("DANUBE_GPIO_P0_OD(0xBE100B24)      = 0x%08X", *(unsigned int *)0xBE100B24);
    dbg("DANUBE_GPIO_P1_OD(0xBE100B54)      = 0x%08X", *(unsigned int *)0xBE100B54);
  #else
    #error Must configure GPIO
  #endif    //  defined(DEBUG_WRITE_GPIO_REGISTER) && DEBUG_WRITE_GPIO_REGISTER
#endif  //  ENABLE_HARDWARE_EMULATION

#if defined(ENABLE_RX_DPLUS_PATH) && ENABLE_RX_DPLUS_PATH
    if ( 1 )
    {
        int i;
        u32 etop_cfg;
        u32 mac_cfg;
        u32 ig_plen_ctrl0;
        u32 mdio_cfg;

        etop_cfg      = *ETOP_CFG;
 *((volatile u32 *)(0xBF203000 + 0x0010)) |= (1 << 8);
        for ( i = 0; i < 0x1000; i++ );
        *ETOP_MDIO_CFG      = mdio_cfg;
        *ETOP_IG_PLEN_CTRL0 = ig_plen_ctrl0;
        *ENET_MAC_CFG(0)    = mac_cfg;
        *ETOP_CFG           = (etop_cfg | 0x01) & ~((1 << 6) | (1 << 8));
    }
#endif

    //  Stop fetching and sending
#if !defined(ENABLE_RX_DPLUS_PATH) || !ENABLE_RX_DPLUS_PATH
    *ETOP_CFG = (*ETOP_CFG | ETOP_CFG_MII1_OFF(1)) & ~(ETOP_CFG_SEN1_ON(1) | ETOP_CFG_FEN1_ON(1));
#else
    *ETOP_CFG = (*ETOP_CFG | ETOP_CFG_MII1_OFF(1) | 0x01) & ~(ETOP_CFG_SEN1_ON(1) | ETOP_CFG_FEN1_ON(1) | (1 << 6) | (1 << 8)); //  Stop both eth0 and eth1
#endif

    //  Set min/max packet size
//    *ETOP_IG_PLEN_CTRL0 = ETOP_IG_PLEN_CTRL0_UNDER_SET(rx_min_packet_size) | ETOP_IG_PLEN_CTRL0_OVER_SET(rx_max_packet_size - ETH_MAC_HEADER_LENGTH);

#if 0   //  Qi Ming has disabled MDIO already in switch driver
    //  Disable MDIO
    ETOP_MDIO_CFG = 0x00;

    //  Enable CRC generation
    ENET_MAC_CFG_CRC_ON(1);

    //  Full Duplex
    ENET_MAC_CFG_DUPLEX_FULL(1);

    //  100M
    ENET_MAC_CFG_SPEED_100M(1);
#else
    *ENET_MAC_CFG(1) = 0x080F;  //  CRC, Egress Pause Frame, Full Duplex, 100M, Link On
//    *ENET_MAC_CFG(1) = 0x0807;  //  CRC, Full Duplex, 100M, Link On
#endif

    //  Configure 2nd ETH device
    *ENETS_DBA(1)     = ENETS1_DBA_DEFAULT;
    *ENETS_CBA(1)     = ENETS1_CBA_DEFAULT;
#if !defined(ENABLE_RX_DPLUS_PATH) || !ENABLE_RX_DPLUS_PATH
    *ENETS_CFG(1)     = ENETS1_CFG_DEFAULT;
#else
    *ENETS_CFG(1)     = 0x506E;
//    *ENETS_PGCNT(0)   = (*ENETS_PGCNT(0) & ~0x0006000) | 0x00020000;
//    *ENETS_PKTCNT(0)  = (*ENETS_PKTCNT(0) & ~0x0600) | 0x0200;  //  PP32 is decrement source
    *ENETF_CBA(1)     = ENETF1_CBA_DEFAULT;
#if 0
    *ENETF_CFG(1)     = ENETF1_CFG_DEFAULT;
#endif
    *ENETF_PGCNT(1)   = ENETF1_PGCNT_DEFAULT;
    *ENETF_PKTCNT(1)  = ENETF1_PKTCNT_DEFAULT;
#if defined(ENABLE_RX_DPLUS_PATH) && ENABLE_RX_DPLUS_PATH
//    *DPLUS_RXCFG      = *DPLUS_RXCFG & ~(1 << 15);  //  0x506E, disable DPLUS
//    *DPLUS_RXPGCNT    = (*DPLUS_RXPGCNT & ~0x00060000) | 0x00040000;    //  PP32 is increment source
    *DPLUS_RXCFG      = 0x506E;
    *DPLUS_RXPGCNT    = 0x00040000;
#endif

    //  Configure share buffer master selection
    *SB_MST_SEL |= 0x03;

    //  Config ETOP
#if defined(ENABLE_TX_CLK_INVERSION) && ENABLE_TX_CLK_INVERSION
    *ETOP_CFG |= ETOP_CFG_TCKINV1_ON(1);
#else
    *ETOP_CFG &= ~ETOP_CFG_TCKINV1_ON(1);
#endif  //  defined(ENABLE_TX_CLK_INVERSION) && ENABLE_TX_CLK_INVERSION
    switch ( mode )
    {
    default:
    case MII_MODE:
        *ETOP_CFG = (*ETOP_CFG & ~ETOP_CFG_MII1_MASK) | ETOP_CFG_MII1_OFF(0) | ETOP_CFG_REV_MII1_ON(0) | ETOP_CFG_TURBO_MII1_ON(0) | ETOP_CFG_SEN1_ON(1) | ETOP_CFG_FEN1_ON(1);
        break;
    case REV_MII_MODE:
        *ETOP_CFG = (*ETOP_CFG & ~ETOP_CFG_MII1_MASK) | ETOP_CFG_MII1_OFF(0) | ETOP_CFG_REV_MII1_ON(1) | ETOP_CFG_TURBO_MII1_ON(0) | ETOP_CFG_SEN1_ON(1) | ETOP_CFG_FEN1_ON(1);
    }
#if defined(ENABLE_RX_DPLUS_PATH) && ENABLE_RX_DPLUS_PATH
    *ETOP_CFG = (*ETOP_CFG & ~0x01) | (1 << 6) | (1 << 8);  //  Start eth0
#endif

    //  Init EMA
    init_ema();

    //  Enable mailbox
#if !defined(ENABLE_RX_DPLUS_PATH) || !ENABLE_RX_DPLUS_PATH
 *MBOX_IGU1_ISRC = 0xFFFFFFFF;
    *MBOX_IGU1_IER  = (1 << RX_TOTAL_CHANNEL_USED) - 1; //  enable RX interrupt only
    *MBOX_IGU3_ISRC = 0xFFFFFFFF;
    *MBOX_IGU3_IER  = ((1 << RX_TOTAL_CHANNEL_USED) - 1) | (((1 << TX_TOTAL_CHANNEL_USED) - 1) << 16);
#else
    *MBOX_IGU1_ISRC = 0xFFFFFFFF;
    *MBOX_IGU1_IER  = 0x00000000;   //  Don't need to enable RX interrupt, DMA driver handle RX path.
    *MBOX_IGU3_ISRC = 0xFFFFFFFF;
    *MBOX_IGU3_IER  = ((1 << TX_TOTAL_CHANNEL_USED) - 1) << 16; //  Never notice PPE firmware with RX event.
#endif

    dbg("ENETS_DBA(0)     = 0x%08X, ENETS_DBA(1)     = 0x%08X", *ENETS_DBA(0),    *ENETS_DBA(1));
    dbg("ENETS_CBA(0)     = 0x%08X, ENETS_CBA(1)     = 0x%08X", *ENETS_CBA(0),    *ENETS_CBA(1));
    dbg("ENETS_CFG(0)     = 0x%08X, ENETS_CFG(1)     = 0x%08X", *ENETS_CFG(0),    *ENETS_CFG(1));
    dbg("ENETS_PGCNT(0)   = 0x%08X, ENETS_PGCNT(1)   = 0x%08X", *ENETS_PGCNT(0),  *ENETS_PGCNT(1));
    dbg("ENETS_PKTCNT(0)  = 0x%08X, ENETS_PKTCNT(1)  = 0x%08X", *ENETS_PKTCNT(0), *ENETS_PKTCNT(1));
    dbg("ENETS_COS_CFG(0) = 0x%08X, ENETS_COS_CFG(1) = 0x%08X", *ENETS_COS_CFG(0),*ENETS_COS_CFG(1));
    dbg("ENETF_DBA(0)     = 0x%08X, ENETF_DBA(1)     = 0x%08X", *ENETF_DBA(0),    *ENETF_DBA(1));
    dbg("ENETF_CBA(0)     = 0x%08X, ENETF_CBA(1)     = 0x%08X", *ENETF_CBA(0),    *ENETF_CBA(1));
    dbg("ENETF_PGCNT(0)   = 0x%08X, ENETF_PGCNT(1)   = 0x%08X", *ENETF_PGCNT(0),  *ENETF_PGCNT(1));
    dbg("ENETF_PKTCNT(0)  = 0x%08X, ENETF_PKTCNT(1)  = 0x%08X", *ENETF_PKTCNT(0), *ENETF_PKTCNT(1));

    dbg("SB_MST_SEL = 0x%08X", *SB_MST_SEL);

    dbg("ETOP_CFG = 0x%08X", *ETOP_CFG);

    dbg("ETOP_IG_PLEN_CTRL0 = 0x%08X", *ETOP_IG_PLEN_CTRL0);

    dbg("ENET_MAC_CFG(0) = 0x%08X, ENET_MAC_CFG(1) = 0x%08X", *ENET_MAC_CFG(0), *ENET_MAC_CFG(1));
}