Index: target/linux/danube/files/arch/mips/danube/dma-core.c =================================================================== --- target/linux/danube/files/arch/mips/danube/dma-core.c (revision 156) +++ target/linux/danube/files/arch/mips/danube/dma-core.c (working copy) @@ -19,7 +19,7 @@ #include #include -#include +#include #include #include #include "dma-core.h" @@ -30,20 +30,20 @@ #define IFX_ERROR 0 #define DANUBE_DMA_WRREG_PROT(chan,addr,value) \ - *DANUBE_DMA_CS=chan; \ - *addr=value; + writel(chan, DANUBE_DMA_CS); \ + writel(value, addr); #define DANUBE_DMA_RDREG_PROT(chan,addr,value) \ - *DANUBE_DMA_CS=chan; \ - value=*addr; + writel(chan, DANUBE_DMA_CS); \ + value=readl(addr); #define DANUBE_DMA_ORREG_PROT(chan,addr,value) \ - *DANUBE_DMA_CS=chan; \ - *addr|=value; + writel(chan, DANUBE_DMA_CS); \ + writel(readl(addr)|value, addr); #define DANUBE_DMA_ANDREG_PROT(chan,addr,value) \ - *DANUBE_DMA_CS=chan; \ - *addr &=value; + writel(chan,DANUBE_DMA_CS); \ + writel(readl(addr) &value, addr); /*25 descriptors for each dma channel,4096/8/20=25.xx*/ #define DANUBE_DMA_DESCRIPTOR_OFFSET 25 @@ -94,57 +94,69 @@ void do_dma_tasklet (unsigned long); DECLARE_TASKLET (dma_tasklet, do_dma_tasklet, 0); -u8* common_buffer_alloc(int len, int *byte_offset, void **opt){ +//TODO +u8* +common_buffer_alloc (int len, int *byte_offset, void **opt) +{ u8 *buffer = (u8 *) kmalloc (len * sizeof (u8), GFP_KERNEL); *byte_offset = 0; return buffer; } - -int common_buffer_free(u8 *dataptr, void *opt){ - if(dataptr) +//TODO +int +common_buffer_free (u8 *dataptr, void *opt) +{ + if (dataptr) kfree(dataptr); return 0; } - -int enable_ch_irq(_dma_channel_info *pCh){ +//TODO +int +enable_ch_irq (_dma_channel_info *pCh) +{ int chan_no = (int)(pCh - dma_chan); int flag; local_irq_save(flag); - *DANUBE_DMA_CS = chan_no; - *DANUBE_DMA_CIE = 0x4a; - *DANUBE_DMA_IRNEN |= 1 << chan_no; + writel(chan_no, DANUBE_DMA_CS); + //TODO + writel(0x4a, DANUBE_DMA_CIE); + writel(readl(DANUBE_DMA_IRNEN) | (1 << chan_no), DANUBE_DMA_IRNEN); local_irq_restore(flag); enable_danube_irq(pCh->irq); return IFX_SUCCESS; } - -int disable_ch_irq(_dma_channel_info *pCh){ +//TODO +int +disable_ch_irq (_dma_channel_info *pCh) +{ int flag; - int chan_num = (int) (pCh - dma_chan); + int chan_no = (int) (pCh - dma_chan); local_irq_save(flag); - g_danube_dma_int_status &= ~(1 << chan_num); - *DANUBE_DMA_CS = chan_num; - *DANUBE_DMA_CIE = 0; - *DANUBE_DMA_IRNEN &= ~(1 << chan_num); + g_danube_dma_int_status &= ~(1 << chan_no); + writel(chan_no, DANUBE_DMA_CS); + writel(0, DANUBE_DMA_CIE); + writel(readl(DANUBE_DMA_IRNEN) & ~(1 << chan_no), DANUBE_DMA_IRNEN); local_irq_restore(flag); mask_and_ack_danube_irq(pCh->irq); return IFX_SUCCESS; } -int open_chan(_dma_channel_info *pCh){ +int +open_chan (_dma_channel_info *pCh) +{ int flag; - int chan_num = (int)(pCh - dma_chan); + int chan_no = (int)(pCh - dma_chan); local_irq_save(flag); - *DANUBE_DMA_CS = chan_num; - *DANUBE_DMA_CCTRL |= 1; + writel(chan_no, DANUBE_DMA_CS); + writel(readl(DANUBE_DMA_CCTRL) | 1, DANUBE_DMA_CCTRL); if(pCh->dir == DANUBE_DMA_RX) enable_ch_irq(pCh); local_irq_restore(flag); @@ -152,29 +164,35 @@ return IFX_SUCCESS; } -int close_chan(_dma_channel_info *pCh){ +int +close_chan(_dma_channel_info *pCh) +{ int flag; - int chan_num = (int) (pCh - dma_chan); + int chan_no = (int) (pCh - dma_chan); local_irq_save(flag); - *DANUBE_DMA_CS = chan_num; - *DANUBE_DMA_CCTRL &= ~1; + writel(chan_no, DANUBE_DMA_CS); + writel(readl(DANUBE_DMA_CCTRL) & ~1, DANUBE_DMA_CCTRL); disable_ch_irq(pCh); local_irq_restore(flag); return IFX_SUCCESS; } -int reset_chan(_dma_channel_info *pCh){ - int chan_num = (int) (pCh - dma_chan); +int +reset_chan (_dma_channel_info *pCh) +{ + int chan_no = (int) (pCh - dma_chan); - *DANUBE_DMA_CS = chan_num; - *DANUBE_DMA_CCTRL |= 2; + writel(chan_no, DANUBE_DMA_CS); + writel(readl(DANUBE_DMA_CCTRL) | 2, DANUBE_DMA_CCTRL); return IFX_SUCCESS; } -void rx_chan_intr_handler(int chan_no){ +void +rx_chan_intr_handler (int chan_no) +{ _dma_device_info *pDev = (_dma_device_info *)dma_chan[chan_no].dma_dev; _dma_channel_info *pCh = &dma_chan[chan_no]; struct rx_desc *rx_desc_p; @@ -203,7 +221,9 @@ } } -inline void tx_chan_intr_handler(int chan_no){ +inline void +tx_chan_intr_handler (int chan_no) +{ _dma_device_info *pDev = (_dma_device_info*)dma_chan[chan_no].dma_dev; _dma_channel_info *pCh = &dma_chan[chan_no]; int tmp; @@ -221,35 +241,45 @@ pDev->intr_handler(pDev, TRANSMIT_CPT_INT); } -void do_dma_tasklet(unsigned long unused){ +void +do_dma_tasklet (unsigned long unused) +{ int i; int chan_no = 0; int budget = DMA_INT_BUDGET; int weight = 0; int flag; - while(g_danube_dma_int_status){ - if(budget-- < 0){ + while (g_danube_dma_int_status) + { + if (budget-- < 0) + { tasklet_schedule(&dma_tasklet); return; } chan_no = -1; weight = 0; - for(i = 0; i < MAX_DMA_CHANNEL_NUM; i++){ - if((g_danube_dma_int_status & (1 << i)) && dma_chan[i].weight > 0){ - if(dma_chan[i].weight > weight){ + for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) + { + if ((g_danube_dma_int_status & (1 << i)) && dma_chan[i].weight > 0) + { + if (dma_chan[i].weight > weight) + { chan_no = i; weight = dma_chan[chan_no].weight; } } } - if(chan_no >= 0){ + + if (chan_no >= 0) + { if (chan_map[chan_no].dir == DANUBE_DMA_RX) rx_chan_intr_handler(chan_no); else tx_chan_intr_handler(chan_no); } else { - for(i = 0; i < MAX_DMA_CHANNEL_NUM; i++){ + for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) + { dma_chan[i].weight = dma_chan[i].default_weight; } } @@ -257,43 +287,53 @@ local_irq_save(flag); g_danube_dma_in_process = 0; - if(g_danube_dma_int_status){ + if (g_danube_dma_int_status) + { g_danube_dma_in_process = 1; tasklet_schedule(&dma_tasklet); } local_irq_restore(flag); } -irqreturn_t dma_interrupt(int irq, void *dev_id){ +irqreturn_t +dma_interrupt (int irq, void *dev_id) +{ _dma_channel_info *pCh; - int chan_num = 0; + int chan_no = 0; int tmp; pCh = (_dma_channel_info*)dev_id; - chan_num = (int)(pCh - dma_chan); - if(chan_num < 0 || chan_num > 19){ + chan_no = (int)(pCh - dma_chan); + if (chan_no < 0 || chan_no > 19) + { BUG(); } tmp = *DANUBE_DMA_IRNEN; *DANUBE_DMA_IRNEN = 0; - g_danube_dma_int_status |= 1 << chan_num; + g_danube_dma_int_status |= 1 << chan_no; *DANUBE_DMA_IRNEN = tmp; mask_and_ack_danube_irq(irq); - if(!g_danube_dma_in_process){ + if (!g_danube_dma_in_process) + { g_danube_dma_in_process = 1; tasklet_schedule(&dma_tasklet); } + return IRQ_HANDLED; } -_dma_device_info* dma_device_reserve(char *dev_name){ +_dma_device_info* +dma_device_reserve (char *dev_name) +{ int i; - for(i = 0; i < MAX_DMA_DEVICE_NUM; i++){ - if(strcmp(dev_name, dma_devs[i].device_name) == 0){ - if(dma_devs[i].reserved) + for (i = 0; i < MAX_DMA_DEVICE_NUM; i++) + { + if (strcmp(dev_name, dma_devs[i].device_name) == 0) + { + if (dma_devs[i].reserved) return NULL; dma_devs[i].reserved = 1; break; @@ -303,13 +343,17 @@ return &dma_devs[i]; } -int dma_device_release(_dma_device_info *dev){ +int +dma_device_release (_dma_device_info *dev) +{ dev->reserved = 0; return IFX_SUCCESS; } -int dma_device_register(_dma_device_info *dev){ +int +dma_device_register(_dma_device_info *dev) +{ int result = IFX_SUCCESS; int i, j; int chan_no = 0; @@ -321,35 +365,41 @@ struct rx_desc *rx_desc_p; struct tx_desc *tx_desc_p; - for(i = 0; i < dev->max_tx_chan_num; i++){ + for (i = 0; i < dev->max_tx_chan_num; i++) + { pCh = dev->tx_chan[i]; - if(pCh->control == DANUBE_DMA_CH_ON){ + if (pCh->control == DANUBE_DMA_CH_ON) + { chan_no = (int)(pCh - dma_chan); - for(j = 0; j < pCh->desc_len; j++){ + for (j = 0; j < pCh->desc_len; j++) + { tx_desc_p = (struct tx_desc*)pCh->desc_base + j; memset(tx_desc_p, 0, sizeof(struct tx_desc)); } local_irq_save(flag); *DANUBE_DMA_CS = chan_no; /*check if the descriptor length is changed */ - if(*DANUBE_DMA_CDLEN != pCh->desc_len) + if (*DANUBE_DMA_CDLEN != pCh->desc_len) *DANUBE_DMA_CDLEN = pCh->desc_len; *DANUBE_DMA_CCTRL &= ~1; *DANUBE_DMA_CCTRL |= 2; - while(*DANUBE_DMA_CCTRL & 2){}; + while (*DANUBE_DMA_CCTRL & 2){}; *DANUBE_DMA_IRNEN |= 1 << chan_no; *DANUBE_DMA_CCTRL = 0x30100; /*reset and enable channel,enable channel later */ local_irq_restore(flag); } } - for(i = 0; i < dev->max_rx_chan_num; i++){ + for (i = 0; i < dev->max_rx_chan_num; i++) + { pCh = dev->rx_chan[i]; - if(pCh->control == DANUBE_DMA_CH_ON){ + if (pCh->control == DANUBE_DMA_CH_ON) + { chan_no = (int)(pCh - dma_chan); - for(j = 0; j < pCh->desc_len; j++){ + for (j = 0; j < pCh->desc_len; j++) + { rx_desc_p = (struct rx_desc*)pCh->desc_base + j; pDev = (_dma_device_info*)(pCh->dma_dev); buffer = pDev->buffer_alloc(pCh->packet_size, &byte_offset, (void*)&(pCh->opt[j])); @@ -369,11 +419,11 @@ local_irq_save(flag); *DANUBE_DMA_CS = chan_no; /*check if the descriptor length is changed */ - if(*DANUBE_DMA_CDLEN != pCh->desc_len) + if (*DANUBE_DMA_CDLEN != pCh->desc_len) *DANUBE_DMA_CDLEN = pCh->desc_len; *DANUBE_DMA_CCTRL &= ~1; *DANUBE_DMA_CCTRL |= 2; - while(*DANUBE_DMA_CCTRL & 2){}; + while (*DANUBE_DMA_CCTRL & 2){}; *DANUBE_DMA_CIE = 0x0A; /*fix me, should enable all the interrupts here? */ *DANUBE_DMA_IRNEN |= 1 << chan_no; *DANUBE_DMA_CCTRL = 0x30000; @@ -385,33 +435,40 @@ return result; } -int dma_device_unregister(_dma_device_info *dev){ +int +dma_device_unregister (_dma_device_info *dev) +{ int result = IFX_SUCCESS; int i, j; - int chan_num; + int chan_no; _dma_channel_info *pCh; struct rx_desc *rx_desc_p; struct tx_desc *tx_desc_p; int flag; - for(i = 0; i < dev->max_tx_chan_num; i++){ + for (i = 0; i < dev->max_tx_chan_num; i++) + { pCh = dev->tx_chan[i]; - if(pCh->control == DANUBE_DMA_CH_ON){ - chan_num = (int)(dev->tx_chan[i] - dma_chan); + if (pCh->control == DANUBE_DMA_CH_ON) + { + chan_no = (int)(dev->tx_chan[i] - dma_chan); local_irq_save (flag); - *DANUBE_DMA_CS = chan_num; + *DANUBE_DMA_CS = chan_no; pCh->curr_desc = 0; pCh->prev_desc = 0; pCh->control = DANUBE_DMA_CH_OFF; *DANUBE_DMA_CIE = 0; /*fix me, should disable all the interrupts here? */ - *DANUBE_DMA_IRNEN &= ~(1 << chan_num); /*disable interrupts */ + *DANUBE_DMA_IRNEN &= ~(1 << chan_no); /*disable interrupts */ *DANUBE_DMA_CCTRL &= ~1; - while(*DANUBE_DMA_CCTRL & 1){}; + while (*DANUBE_DMA_CCTRL & 1) {}; local_irq_restore (flag); - for(j = 0; j < pCh->desc_len; j++){ + for (j = 0; j < pCh->desc_len; j++) + { tx_desc_p = (struct tx_desc*)pCh->desc_base + j; - if((tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C) || (tx_desc_p->status.field.OWN == DMA_OWN && tx_desc_p->status.field.data_length > 0)){ + if ((tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C) + || (tx_desc_p->status.field.OWN == DMA_OWN && tx_desc_p->status.field.data_length > 0)) + { dev->buffer_free ((u8 *) __va (tx_desc_p->Data_Pointer), (void*)pCh->opt[j]); } tx_desc_p->status.field.OWN = CPU_OWN; @@ -421,28 +478,29 @@ } } - for(i = 0; i < dev->max_rx_chan_num; i++){ + for (i = 0; i < dev->max_rx_chan_num; i++) + { pCh = dev->rx_chan[i]; - chan_num = (int)(dev->rx_chan[i] - dma_chan); + chan_no = (int)(dev->rx_chan[i] - dma_chan); disable_danube_irq(pCh->irq); local_irq_save(flag); - g_danube_dma_int_status &= ~(1 << chan_num); + g_danube_dma_int_status &= ~(1 << chan_no); pCh->curr_desc = 0; pCh->prev_desc = 0; pCh->control = DANUBE_DMA_CH_OFF; - *DANUBE_DMA_CS = chan_num; + *DANUBE_DMA_CS = chan_no; *DANUBE_DMA_CIE = 0; /*fix me, should disable all the interrupts here? */ - *DANUBE_DMA_IRNEN &= ~(1 << chan_num); /*disable interrupts */ + *DANUBE_DMA_IRNEN &= ~(1 << chan_no); /*disable interrupts */ *DANUBE_DMA_CCTRL &= ~1; - while (*DANUBE_DMA_CCTRL & 1) { - }; + while (*DANUBE_DMA_CCTRL & 1) {}; local_irq_restore (flag); - for (j = 0; j < pCh->desc_len; j++) { + for (j = 0; j < pCh->desc_len; j++) + { rx_desc_p = (struct rx_desc *) pCh->desc_base + j; - if ((rx_desc_p->status.field.OWN == CPU_OWN + if ((rx_desc_p->status.field.OWN == CPU_OWN && rx_desc_p->status.field.C) || (rx_desc_p->status.field.OWN == DMA_OWN && rx_desc_p->status.field.data_length > 0)) { @@ -457,7 +515,9 @@ return result; } -int dma_device_read(struct dma_device_info *dma_dev, u8 ** dataptr, void **opt){ +int +dma_device_read (struct dma_device_info *dma_dev, u8 ** dataptr, void **opt) +{ u8 *buf; int len; int byte_offset = 0; @@ -467,7 +527,8 @@ /*get the rx data first */ rx_desc_p = (struct rx_desc *) pCh->desc_base + pCh->curr_desc; - if(!(rx_desc_p->status.field.OWN == CPU_OWN && rx_desc_p->status.field.C)){ + if (!(rx_desc_p->status.field.OWN == CPU_OWN && rx_desc_p->status.field.C)) + { return 0; } @@ -475,14 +536,16 @@ *(u32*)dataptr = (u32)buf; len = rx_desc_p->status.field.data_length; - if(opt){ + if (opt) + { *(int*)opt = (int)pCh->opt[pCh->curr_desc]; } /*replace with a new allocated buffer */ buf = dma_dev->buffer_alloc(pCh->packet_size, &byte_offset, &p); - if(buf){ + if (buf) + { #ifndef CONFIG_MIPS_UNCACHED /* tc.chen: invalidate cache */ dma_cache_inv ((unsigned long) buf, @@ -494,8 +557,7 @@ rx_desc_p->Data_Pointer = (u32) CPHYSADDR ((u32) buf); rx_desc_p->status.word = (DMA_OWN << 31) | ((byte_offset) << 23) | pCh->packet_size; wmb (); - } - else { + } else { *(u32 *) dataptr = 0; if (opt) *(int *) opt = 0; @@ -504,13 +566,15 @@ /*increase the curr_desc pointer */ pCh->curr_desc++; - if(pCh->curr_desc == pCh->desc_len) + if (pCh->curr_desc == pCh->desc_len) pCh->curr_desc = 0; return len; } -int dma_device_write (struct dma_device_info *dma_dev, u8 * dataptr, int len, void *opt){ +int +dma_device_write (struct dma_device_info *dma_dev, u8 * dataptr, int len, void *opt) +{ int flag; u32 tmp, byte_offset; _dma_channel_info *pCh; @@ -522,7 +586,8 @@ chan_no = (int)(pCh - (_dma_channel_info *) dma_chan); tx_desc_p = (struct tx_desc*)pCh->desc_base + pCh->prev_desc; - while(tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C){ + while (tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C) + { dma_dev->buffer_free((u8 *) __va (tx_desc_p->Data_Pointer), pCh->opt[pCh->prev_desc]); memset(tx_desc_p, 0, sizeof (struct tx_desc)); pCh->prev_desc = (pCh->prev_desc + 1) % (pCh->desc_len); @@ -530,7 +595,8 @@ } tx_desc_p = (struct tx_desc*)pCh->desc_base + pCh->curr_desc; /*Check whether this descriptor is available */ - if(tx_desc_p->status.field.OWN == DMA_OWN || tx_desc_p->status.field.C){ + if (tx_desc_p->status.field.OWN == DMA_OWN || tx_desc_p->status.field.C) + { /*if not , the tell the upper layer device */ dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT); local_irq_restore(flag); @@ -557,12 +623,13 @@ /*Check whether this descriptor is available */ tx_desc_p = (struct tx_desc *) pCh->desc_base + pCh->curr_desc; - if (tx_desc_p->status.field.OWN == DMA_OWN) { + if (tx_desc_p->status.field.OWN == DMA_OWN) + { /*if not , the tell the upper layer device */ dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT); } DANUBE_DMA_RDREG_PROT(chan_no, DANUBE_DMA_CCTRL, tmp); - if(!(tmp & 1)) + if (!(tmp & 1)) pCh->open (pCh); local_irq_restore (flag); @@ -570,25 +637,32 @@ return len; } -int map_dma_chan(_dma_chan_map *map){ +int +map_dma_chan(_dma_chan_map *map) +{ int i, j; int result; - for(i = 0; i < MAX_DMA_DEVICE_NUM; i++){ + for (i = 0; i < MAX_DMA_DEVICE_NUM; i++) + { strcpy(dma_devs[i].device_name, global_device_name[i]); } - for(i = 0; i < MAX_DMA_CHANNEL_NUM; i++){ + for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) + { dma_chan[i].irq = map[i].irq; result = request_irq(dma_chan[i].irq, dma_interrupt, SA_INTERRUPT, "dma-core", (void*)&dma_chan[i]); - if(result){ + if (result) + { printk("error, cannot get dma_irq!\n"); free_irq(dma_chan[i].irq, (void *) &dma_interrupt); + return -EFAULT; } } - for(i = 0; i < MAX_DMA_DEVICE_NUM; i++){ + for (i = 0; i < MAX_DMA_DEVICE_NUM; i++) + { dma_devs[i].num_tx_chan = 0; /*set default tx channel number to be one */ dma_devs[i].num_rx_chan = 0; /*set default rx channel number to be one */ dma_devs[i].max_rx_chan_num = 0; @@ -598,17 +672,20 @@ dma_devs[i].intr_handler = NULL; dma_devs[i].tx_burst_len = 4; dma_devs[i].rx_burst_len = 4; - if (i == 0) { + if (i == 0) + { *DANUBE_DMA_PS = 0; *DANUBE_DMA_PCTRL |= (0xf << 8) | (1 << 6); /*enable dma drop */ } - if (i == 1) { + if (i == 1) + { *DANUBE_DMA_PS = 1; *DANUBE_DMA_PCTRL = 0x14; /*deu port setting */ } - for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++) { + for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++) + { dma_chan[j].byte_offset = 0; dma_chan[j].open = &open_chan; dma_chan[j].close = &close_chan; @@ -623,22 +700,27 @@ dma_chan[j].prev_desc = 0; } - for(j = 0; j < MAX_DMA_CHANNEL_NUM; j++){ - if(strcmp(dma_devs[i].device_name, map[j].dev_name) == 0) { - if (map[j].dir == DANUBE_DMA_RX) { + for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++) + { + if (strcmp(dma_devs[i].device_name, map[j].dev_name) == 0) + { + if (map[j].dir == DANUBE_DMA_RX) + { dma_chan[j].dir = DANUBE_DMA_RX; dma_devs[i].max_rx_chan_num++; dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1] = &dma_chan[j]; dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1]->pri = map[j].pri; dma_chan[j].dma_dev = (void*)&dma_devs[i]; - } else if(map[j].dir == DANUBE_DMA_TX){ /*TX direction */ + } else if(map[j].dir == DANUBE_DMA_TX) + { /*TX direction */ dma_chan[j].dir = DANUBE_DMA_TX; dma_devs[i].max_tx_chan_num++; dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1] = &dma_chan[j]; dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1]->pri = map[j].pri; dma_chan[j].dma_dev = (void*)&dma_devs[i]; - } else - printk ("WRONG MAP!\n"); + } else { + printk ("WRONG DMA MAP!\n"); + } } } } @@ -646,11 +728,13 @@ return IFX_SUCCESS; } -int dma_chip_init(void){ +int +dma_chip_init(void) +{ int i; // enable DMA from PMU - *DANUBE_PMU_PWDCR &= ~(1 << DANUBE_PMU_DMA_SHIFT); + *DANUBE_PMU_PWDCR &= ~(DANUBE_PMU_PWDCR_DMA); // reset DMA *DANUBE_DMA_CTRL |= 1; @@ -658,24 +742,26 @@ // diable all interrupts *DANUBE_DMA_IRNEN = 0; - for(i = 0; i < MAX_DMA_CHANNEL_NUM; i++){ + for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) + { *DANUBE_DMA_CS = i; *DANUBE_DMA_CCTRL = 0x2; *DANUBE_DMA_CPOLL = 0x80000040; // set memcopy channel class - if(i == 8 || i == 9) + if (i == 8 || i == 9) *DANUBE_DMA_CCTRL = (*DANUBE_DMA_CCTRL & (~(3 << 9))); - if(i == 10 || i == 11) + if (i == 10 || i == 11) *DANUBE_DMA_CCTRL = (*DANUBE_DMA_CCTRL & (~(3 << 9))) | (1 << 9); // set memcopy channel class - if(i == 16 || i == 17) + if (i == 16 || i == 17) *DANUBE_DMA_CCTRL = (*DANUBE_DMA_CCTRL | (3 << 9)); - if(i == 18 || i == 19) + if (i == 18 || i == 19) *DANUBE_DMA_CCTRL = (*DANUBE_DMA_CCTRL & (~(3 << 9))) | (1 << 9); } - for(i = 0; i < MAX_DMA_CHANNEL_NUM; i++){ + for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) + { // per default all channels are turned off *DANUBE_DMA_CS = i; *DANUBE_DMA_CCTRL &= ~1; @@ -684,21 +770,25 @@ return IFX_SUCCESS; } -int danube_dma_init(void){ +int +danube_dma_init (void) +{ int i; dma_chip_init(); map_dma_chan(default_dma_map); g_desc_list = (u64*)KSEG1ADDR(__get_free_page(GFP_DMA)); - if(g_desc_list == NULL){ + if (g_desc_list == NULL) + { printk("no memory for desriptor\n"); return -ENOMEM; } memset (g_desc_list, 0, PAGE_SIZE); - for(i = 0; i < MAX_DMA_CHANNEL_NUM; i++){ + for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) + { dma_chan[i].desc_base = (u32)g_desc_list + i * DANUBE_DMA_DESCRIPTOR_OFFSET * 8; dma_chan[i].curr_desc = 0; dma_chan[i].desc_len = DANUBE_DMA_DESCRIPTOR_OFFSET; @@ -712,11 +802,13 @@ arch_initcall(danube_dma_init); -void dma_cleanup(void){ +void +dma_cleanup(void) +{ int i; free_page(KSEG0ADDR((unsigned long) g_desc_list)); - for(i = 0; i < MAX_DMA_CHANNEL_NUM; i++) + for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) free_irq(dma_chan[i].irq, (void*)&dma_interrupt); }