library std;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.numeric_std.all;
use std.textio.all;

entity mux is
port ( 
	mux_sel			: in 	std_logic_vector(1 downto 0);
	a,b,c,d			: in 	std_logic_vector(7 downto 0);
	mux_out			: out	std_logic_vector(7 downto 0)
);
end entity;

architecture struct of mux is

begin
	process( mux_sel,a,b,c,d )
	begin
		case mux_sel is
		when "00" 		=> mux_out	<= a;
		when "01" 		=> mux_out	<= b;
		when "10" 		=> mux_out	<= c;
		when others 	=> mux_out	<= d;
		end case;
	end process;

end architecture;



Reading design: mux.prj

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "/home/peterzal/junk/wp_mux.vhdl" in Library work.
Entity <mux> compiled.
Entity <mux> (Architecture <struct>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <mux> in library <work> (architecture <struct>).


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <mux> in library <work> (Architecture <struct>).
Entity <mux> analyzed. Unit <mux> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <mux>.
    Related source file is "/home/peterzal/junk/wp_mux.vhdl".
    Found 8-bit 4-to-1 multiplexer for signal <mux_out>.
    Summary:
	inferred   8 Multiplexer(s).
Unit <mux> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Multiplexers                                         : 1
 8-bit 4-to-1 multiplexer                              : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Loading device for application Rf_Device from file '4vfx60.nph' in environment /home/peterzal/Xilinx91i.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Multiplexers                                         : 1
 8-bit 4-to-1 multiplexer                              : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <mux> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block mux, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Found no macro
=========================================================================

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================

Clock Information:
------------------
No clock signals found in this design

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -11

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 6.113ns

=========================================================================
WARNING:ProjectMgmt - "/home/peterzal/windoze/doot/parts/mux.ngc" line 0 duplicate design unit: 'Module|mux'

Process "Synthesize" completed successfully