Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "crc_32.v"
Module <crc_32> compiled
Compiling source file "crc_tb.v"
Module <crc_tb> compiled
No errors in compilation
Analysis of file <crc_tb.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <crc_tb>.
WARNING:Xst:854 - crc_tb.v line 8: Ignored initial statement.
Module <crc_tb> is correct for synthesis.
 
Analyzing module <crc_32>.
WARNING:Xst:854 - crc_32.v line 9: Ignored initial statement.
Module <crc_32> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <crc_32>.
    Related source file is crc_32.v.
WARNING:Xst:647 - Input <data_in> is never used.
WARNING:Xst:1780 - Signal <crc<31:8>> is never used or assigned.
WARNING:Xst:653 - Signal <crc<7:0>> is used but never assigned. Tied to value 11111111.
WARNING:Xst:1872 - Variable <i> is used but never assigned.
WARNING:Xst:1780 - Signal <crc_32_ieee> is never used or assigned.
Unit <crc_32> synthesized.


Synthesizing Unit <crc_tb>.
    Related source file is crc_tb.v.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:646 - Signal <crc_out> is assigned but never used.
WARNING:Xst:653 - Signal <data_in> is used but never assigned. Tied to value 00000000.
Unit <crc_tb> synthesized.

WARNING:Xst:524 - All outputs of the instance <c1> of the block <crc_32> are unconnected in block <crc_tb>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <crc_tb> ...
Loading device for application Xst from file '3s400.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block crc_tb, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 



=========================================================================
TIMING REPORT


Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".