k_static.vhdl
Number of Slices:                     322  out of  25280     1%
Number of 4 input LUTs:               572  out of  50560     1%
Maximum combinational path delay: 9.266ns

mux_128_to_64.vhdl
Number of Slices:                      37  out of  25280     0%
Number of 4 input LUTs:                64  out of  50560     0%
Maximum combinational path delay: 6.188ns

sha512_comp_unit.vhdl
Number of Slices:                    1125  out of  25280     4%
Number of Slice Flip Flops:           512  out of  50560     1%
Minimum period: 8.620ns (Maximum Frequency: 116.009MHz)

sha512_control_unit.vhdl
Number of Slices:                      83  out of  25280     0%
Number of Slice Flip Flops:            54  out of  50560     0%
Minimum period: 3.882ns (Maximum Frequency: 257.599MHz)

sha512_exp_unit.vhdl
Number of Slices:                     399  out of  25280     1%
Number of Slice Flip Flops:           448  out of  50560     0%
Minimum period: 6.782ns (Maximum Frequency: 147.449MHz)

sha512_hu_unit.vhdl
Number of Slices:                     552  out of  25280     2%
Number of Slice Flip Flops:           512  out of  50560     1%
Minimum period: 4.875ns (Maximum Frequency: 205.128MHz)

sha512_struct.vhdl
Number of Slices:                    1999  out of  25280     7%
Number of Slice Flip Flops:          1578  out of  50560     3%
Number of 4 input LUTs:              3728  out of  50560     7%
Number used as logic:             3535
Number used as Shift registers:    193
~