architecture behaviour of ADR is
     begin
          process(Takt)
               if reset = '1' then PC <= "000000";
               elsif Takt = '1' then
                    if count = '1' then
                         PC <= PC + '1';
                    elsif branch = '1' then
                         PC <= PC + offset;
                    end if;
               end if;
          end;
end architecture behaviour;